static void timer_write(void *opaque, target_phys_addr_t addr, uint32_t value)
{
LM32TimerState *s = opaque;
trace_lm32_timer_memory_write(addr, value);
addr >>= 2;
switch (addr) {
case R_SR:
s->regs[R_SR] &= ~SR_TO;
break;
case R_CR:
s->regs[R_CR] = value;
if (s->regs[R_CR] & CR_START) {
ptimer_run(s->ptimer, 1);
}
if (s->regs[R_CR] & CR_STOP) {
ptimer_stop(s->ptimer);
}
break;
case R_PERIOD:
s->regs[R_PERIOD] = value;
ptimer_set_count(s->ptimer, value);
break;
case R_SNAPSHOT:
error_report("lm32_timer: write access to read only register 0x"
TARGET_FMT_plx, addr << 2);
break;
default:
error_report("lm32_timer: write access to unknown register 0x"
TARGET_FMT_plx, addr << 2);
break;
}
timer_update_irq(s);
}
static void
timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct timerblock *t = opaque;
struct xlx_timer *xt;
unsigned int timer;
uint32_t value = val64;
addr >>= 2;
timer = timer_from_addr(addr);
xt = &t->timers[timer];
D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
__func__, addr * 4, value, timer, addr & 3));
/* Further decoding to address a specific timers reg. */
addr &= 3;
switch (addr)
{
case R_TCSR:
if (value & TCSR_TINT)
value &= ~TCSR_TINT;
xt->regs[addr] = value & 0x7ff;
if (value & TCSR_ENT)
timer_enable(xt);
break;
default:
if (addr < ARRAY_SIZE(xt->regs))
xt->regs[addr] = value;
break;
}
timer_update_irq(t);
}
static void
timer_write(void *opaque, hwaddr addr,
uint64_t val64, unsigned int size)
{
struct etrax_timer *t = opaque;
uint32_t value = val64;
switch (addr)
{
case RW_TMR0_DIV:
t->rw_tmr0_div = value;
break;
case RW_TMR0_CTRL:
D(printf ("RW_TMR0_CTRL=%x\n", value));
t->rw_tmr0_ctrl = value;
update_ctrl(t, 0);
break;
case RW_TMR1_DIV:
t->rw_tmr1_div = value;
break;
case RW_TMR1_CTRL:
D(printf ("RW_TMR1_CTRL=%x\n", value));
t->rw_tmr1_ctrl = value;
update_ctrl(t, 1);
break;
case RW_INTR_MASK:
D(printf ("RW_INTR_MASK=%x\n", value));
t->rw_intr_mask = value;
timer_update_irq(t);
break;
case RW_WD_CTRL:
timer_watchdog_update(t, value);
break;
case RW_ACK_INTR:
t->rw_ack_intr = value;
timer_update_irq(t);
t->rw_ack_intr = 0;
break;
default:
printf ("%s " TARGET_FMT_plx " %x\n",
__func__, addr, value);
break;
}
}
static void timer_hit(void *opaque)
{
struct xlx_timer *xt = opaque;
struct timerblock *t = xt->parent;
D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
xt->regs[R_TCSR] |= TCSR_TINT;
if (xt->regs[R_TCSR] & TCSR_ARHT)
timer_enable(xt);
timer_update_irq(t);
}
static void timer_hit(void *opaque)
{
struct Msf2Timer *st = opaque;
st->regs[R_TIM_RIS] |= TIMER_RIS_ACK;
if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) {
timer_update(st);
}
timer_update_irq(st);
}
static void timer_hit(void *opaque)
{
LM32TimerState *s = opaque;
trace_lm32_timer_hit();
s->regs[R_SR] |= SR_TO;
if (s->regs[R_CR] & CR_CONT) {
ptimer_set_count(s->ptimer, s->regs[R_PERIOD]);
ptimer_run(s->ptimer, 1);
}
timer_update_irq(s);
}
static void timer1_hit(void *opaque)
{
struct etrax_timer *t = opaque;
t->r_intr |= 2;
timer_update_irq(t);
}
static void
timer_write(void *opaque, hwaddr offset,
uint64_t val64, unsigned int size)
{
MSSTimerState *t = opaque;
hwaddr addr;
struct Msf2Timer *st;
int timer = 0;
uint32_t value = val64;
addr = offset >> 2;
/*
* Two independent timers has same base address.
* Based on addr passed figure out which timer is being used.
*/
if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) {
timer = 1;
addr -= R_TIM1_MAX;
}
st = &t->timers[timer];
DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset,
value, timer);
switch (addr) {
case R_TIM_CTRL:
st->regs[R_TIM_CTRL] = value;
timer_update(st);
break;
case R_TIM_RIS:
if (value & TIMER_RIS_ACK) {
st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK;
}
break;
case R_TIM_LOADVAL:
st->regs[R_TIM_LOADVAL] = value;
if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) {
timer_update(st);
}
break;
case R_TIM_BGLOADVAL:
st->regs[R_TIM_BGLOADVAL] = value;
st->regs[R_TIM_LOADVAL] = value;
break;
case R_TIM_VAL:
case R_TIM_MIS:
break;
default:
if (addr < R_TIM1_MAX) {
st->regs[addr] = value;
} else {
qemu_log_mask(LOG_GUEST_ERROR,
TYPE_MSS_TIMER": 64-bit mode not supported\n");
return;
}
break;
}
timer_update_irq(st);
}