static void * vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx, const struct pipe_depth_stencil_alpha_state *cso) { struct vc4_depth_stencil_alpha_state *so; so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state); if (!so) return NULL; so->base = *cso; if (cso->depth.enabled) { if (cso->depth.writemask) { so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; } so->config_bits[1] |= (cso->depth.func << VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT); } else { so->config_bits[1] |= (PIPE_FUNC_ALWAYS << VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT); } if (cso->stencil[0].enabled) { const struct pipe_stencil_state *front = &cso->stencil[0]; const struct pipe_stencil_state *back = &cso->stencil[1]; uint8_t front_writemask_bits = tlb_stencil_setup_writemask(front->writemask); uint8_t back_writemask = front->writemask; uint8_t back_writemask_bits = front_writemask_bits; so->stencil_uniforms[0] = tlb_stencil_setup_bits(front, front_writemask_bits); if (back->enabled) { back_writemask = back->writemask; back_writemask_bits = tlb_stencil_setup_writemask(back->writemask); so->stencil_uniforms[0] |= (1 << 30); so->stencil_uniforms[1] = tlb_stencil_setup_bits(back, back_writemask_bits); so->stencil_uniforms[1] |= (2 << 30); } else { so->stencil_uniforms[0] |= (3 << 30); } if (front_writemask_bits == 0xff || back_writemask_bits == 0xff) { so->stencil_uniforms[2] = (front->writemask | (back_writemask << 8)); } } return so; }
static void * vc4_create_depth_stencil_alpha_state(struct pipe_context *pctx, const struct pipe_depth_stencil_alpha_state *cso) { struct vc4_depth_stencil_alpha_state *so; so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state); if (!so) return NULL; so->base = *cso; /* We always keep the early Z state correct, since a later state using * early Z may want it. */ so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; if (cso->depth.enabled) { if (cso->depth.writemask) { so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; } so->config_bits[1] |= (cso->depth.func << VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT); /* We only handle early Z in the < direction because otherwise * we'd have to runtime guess which direction to set in the * render config. */ if ((cso->depth.func == PIPE_FUNC_LESS || cso->depth.func == PIPE_FUNC_LEQUAL) && (!cso->stencil[0].enabled || (cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP && (!cso->stencil[1].enabled || cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP)))) { so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; } } else { so->config_bits[1] |= (PIPE_FUNC_ALWAYS << VC4_CONFIG_BITS_DEPTH_FUNC_SHIFT); } if (cso->stencil[0].enabled) { const struct pipe_stencil_state *front = &cso->stencil[0]; const struct pipe_stencil_state *back = &cso->stencil[1]; uint8_t front_writemask_bits = tlb_stencil_setup_writemask(front->writemask); uint8_t back_writemask = front->writemask; uint8_t back_writemask_bits = front_writemask_bits; so->stencil_uniforms[0] = tlb_stencil_setup_bits(front, front_writemask_bits); if (back->enabled) { back_writemask = back->writemask; back_writemask_bits = tlb_stencil_setup_writemask(back->writemask); so->stencil_uniforms[0] |= (1 << 30); so->stencil_uniforms[1] = tlb_stencil_setup_bits(back, back_writemask_bits); so->stencil_uniforms[1] |= (2 << 30); } else { so->stencil_uniforms[0] |= (3 << 30); } if (front_writemask_bits == 0xff || back_writemask_bits == 0xff) { so->stencil_uniforms[2] = (front->writemask | (back_writemask << 8)); } } return so; }