static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); writel(0, lpc32xx->base + (pwm->hwpwm << 2)); clk_disable(lpc32xx->clk); }
static void lpc32xx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); u32 val; val = readl(lpc32xx->base + (pwm->hwpwm << 2)); val &= ~PWM_ENABLE; writel(val, lpc32xx->base + (pwm->hwpwm << 2)); clk_disable(lpc32xx->clk); }
static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); u32 val; int ret; ret = clk_enable(lpc32xx->clk); if (ret) return ret; val = readl(lpc32xx->base + (pwm->hwpwm << 2)); val |= PWM_ENABLE; writel(val, lpc32xx->base + (pwm->hwpwm << 2)); return 0; }
static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); unsigned long long c; int period_cycles, duty_cycles; u32 val; c = clk_get_rate(lpc32xx->clk) / 256; c = c * period_ns; do_div(c, NSEC_PER_SEC); /* Handle high and low extremes */ if (c == 0) c = 1; if (c > 255) c = 0; /* 0 set division by 256 */ period_cycles = c; /* The duty-cycle value is as follows: * * DUTY-CYCLE HIGH LEVEL * 1 99.9% * 25 90.0% * 128 50.0% * 220 10.0% * 255 0.1% * 0 0.0% * * In other words, the register value is duty-cycle % 256 with * duty-cycle in the range 1-256. */ c = 256 * duty_ns; do_div(c, period_ns); if (c > 255) c = 255; duty_cycles = 256 - c; val = readl(lpc32xx->base + (pwm->hwpwm << 2)); val &= ~0xFFFF; val |= PWM_RELOADV(period_cycles) | PWM_DUTY(duty_cycles); writel(val, lpc32xx->base + (pwm->hwpwm << 2)); return 0; }
static int lpc32xx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) { struct lpc32xx_pwm_chip *lpc32xx = to_lpc32xx_pwm_chip(chip); return clk_enable(lpc32xx->clk); }