static void wl12xx_spi_init(struct device *child)
{
struct wl12xx_spi_glue *glue = dev_get_drvdata(child->parent);
u8 crc[WSPI_INIT_CMD_CRC_LEN], *cmd;
struct spi_transfer t;
struct spi_message m;
cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
if (!cmd) {
dev_err(child->parent,
"could not allocate cmd for spi init\n");
return;
}
memset(crc, 0, sizeof(crc));
memset(&t, 0, sizeof(t));
spi_message_init(&m);
/*
* Set WSPI_INIT_COMMAND
* the data is being send from the MSB to LSB
*/
cmd[2] = 0xff;
cmd[3] = 0xff;
cmd[1] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
cmd[0] = 0;
cmd[7] = 0;
cmd[6] |= HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
cmd[6] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
cmd[5] |= WSPI_INIT_CMD_DIS_FIXEDBUSY;
else
cmd[5] |= WSPI_INIT_CMD_EN_FIXEDBUSY;
cmd[5] |= WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
| WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;
crc[0] = cmd[1];
crc[1] = cmd[0];
crc[2] = cmd[7];
crc[3] = cmd[6];
crc[4] = cmd[5];
cmd[4] |= crc7(0, crc, WSPI_INIT_CMD_CRC_LEN) << 1;
cmd[4] |= WSPI_INIT_CMD_END;
t.tx_buf = cmd;
t.len = WSPI_INIT_CMD_LEN;
spi_message_add_tail(&t, &m);
spi_sync(to_spi_device(glue->dev), &m);
kfree(cmd);
}
/* SPI bustype and spi_master class are registered after board init code
* provides the SPI device tables, ensuring that both are present by the
* time controller driver registration causes spi_devices to "enumerate".
*/
static void spidev_release(struct device *dev)
{
const struct spi_device *spi = to_spi_device(dev);
/* spi masters may cleanup for released devices */
if (spi->master->cleanup)
spi->master->cleanup(spi);
spi_master_put(spi->master);
kfree(dev);
}
int touch_bus_write(struct device *dev, struct touch_bus_msg *msg)
{
struct touch_core_data *ts = to_touch_core(dev);
int ret = 0;
if (ts->bus_type == HWIF_I2C)
ret = touch_i2c_write(to_i2c_client(dev), msg);
else if (ts->bus_type == HWIF_SPI)
ret = touch_spi_write(to_spi_device(dev), msg);
return ret;
}
static int ds3234_set_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
/* MSB must be '1' to indicate write */
buf[0] = address | 0x80;
buf[1] = data;
return spi_write_then_read(spi, buf, 2, NULL, 0);
}
static int serial_m3110_resume(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
struct uart_max3110 *max = spi_get_drvdata(spi);
/* Enable IRQ before max3110 write */
if (max->irq > 0)
enable_irq(max->irq);
max3110_out(max, max->cur_conf);
uart_resume_port(&serial_m3110_reg, &max->port);
return 0;
}
static void max6902_set_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
/* MSB must be '0' to write */
buf[0] = address & 0x7f;
buf[1] = data;
spi_write(spi, buf, 2);
}
static int max6902_set_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
/* MSB must be '0' to write */
buf[0] = address & 0x7f;
buf[1] = data;
return spi_write_then_read(spi, buf, 2, NULL, 0);
}
static void adau1781_spi_switch_mode(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
/*
* To get the device into SPI mode CLATCH has to be pulled low three
* times. Do this by issuing three dummy reads.
*/
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
spi_w8r8(spi, 0x00);
}
static int ssp_resume(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
struct ssp_data *data = spi_get_drvdata(spi);
if (data->bSspShutdown == false) {
func_dbg();
enable_irq(data->iIrq);
}
return 0;
}
static void ds1390_set_reg(struct device *dev, unsigned char address,
unsigned char data)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char buf[2];
/* MSB must be '1' to write */
buf[0] = address | 0x80;
buf[1] = data;
spi_write(spi, buf, 2);
}
static int adxl34x_spi_read_block(struct device *dev,
unsigned char reg, int count,
void *buf)
{
struct spi_device *spi = to_spi_device(dev);
ssize_t status;
reg = ADXL34X_READMB_CMD(reg);
status = spi_write_then_read(spi, ®, 1, buf, count);
return (status < 0) ? status : 0;
}
static void wl12xx_spi_init(struct device *child)
{
struct wl12xx_spi_glue *glue = dev_get_drvdata(child->parent);
struct spi_transfer t;
struct spi_message m;
u8 *cmd = kzalloc(WSPI_INIT_CMD_LEN, GFP_KERNEL);
if (!cmd) {
dev_err(child->parent,
"could not allocate cmd for spi init\n");
return;
}
memset(&t, 0, sizeof(t));
spi_message_init(&m);
/*
* Set WSPI_INIT_COMMAND
* the data is being send from the MSB to LSB
*/
cmd[0] = 0xff;
cmd[1] = 0xff;
cmd[2] = WSPI_INIT_CMD_START | WSPI_INIT_CMD_TX;
cmd[3] = 0;
cmd[4] = 0;
cmd[5] = HW_ACCESS_WSPI_INIT_CMD_MASK << 3;
cmd[5] |= HW_ACCESS_WSPI_FIXED_BUSY_LEN & WSPI_INIT_CMD_FIXEDBUSY_LEN;
cmd[6] = WSPI_INIT_CMD_IOD | WSPI_INIT_CMD_IP | WSPI_INIT_CMD_CS
| WSPI_INIT_CMD_WSPI | WSPI_INIT_CMD_WS;
if (HW_ACCESS_WSPI_FIXED_BUSY_LEN == 0)
cmd[6] |= WSPI_INIT_CMD_DIS_FIXEDBUSY;
else
cmd[6] |= WSPI_INIT_CMD_EN_FIXEDBUSY;
cmd[7] = crc7_be(0, cmd+2, WSPI_INIT_CMD_CRC_LEN) | WSPI_INIT_CMD_END;
/*
* The above is the logical order; it must actually be stored
* in the buffer byte-swapped.
*/
__swab32s((u32 *)cmd);
__swab32s((u32 *)cmd+1);
t.tx_buf = cmd;
t.len = WSPI_INIT_CMD_LEN;
spi_message_add_tail(&t, &m);
spi_sync(to_spi_device(glue->dev), &m);
kfree(cmd);
}
static int __must_check wl12xx_spi_raw_write(struct device *child, int addr,
void *buf, size_t len, bool fixed)
{
struct wl12xx_spi_glue *glue = dev_get_drvdata(child->parent);
/* SPI write buffers - 2 for each chunk */
struct spi_transfer t[2 * WSPI_MAX_NUM_OF_CHUNKS];
struct spi_message m;
u32 commands[WSPI_MAX_NUM_OF_CHUNKS]; /* 1 command per chunk */
u32 *cmd;
u32 chunk_len;
int i;
WARN_ON(len > SPI_AGGR_BUFFER_SIZE);
spi_message_init(&m);
memset(t, 0, sizeof(t));
cmd = &commands[0];
i = 0;
while (len > 0) {
chunk_len = min_t(size_t, WSPI_MAX_CHUNK_SIZE, len);
*cmd = 0;
*cmd |= WSPI_CMD_WRITE;
*cmd |= (chunk_len << WSPI_CMD_BYTE_LENGTH_OFFSET) &
WSPI_CMD_BYTE_LENGTH;
*cmd |= addr & WSPI_CMD_BYTE_ADDR;
if (fixed)
*cmd |= WSPI_CMD_FIXED;
t[i].tx_buf = cmd;
t[i].len = sizeof(*cmd);
spi_message_add_tail(&t[i++], &m);
t[i].tx_buf = buf;
t[i].len = chunk_len;
spi_message_add_tail(&t[i++], &m);
if (!fixed)
addr += chunk_len;
buf += chunk_len;
len -= chunk_len;
cmd++;
}
spi_sync(to_spi_device(glue->dev), &m);
return 0;
}
int touch_bus_xfer(struct device *dev, struct touch_xfer_msg *xfer)
{
struct touch_core_data *ts = to_touch_core(dev);
int ret = 0;
if (ts->bus_type == HWIF_I2C) {
TOUCH_E("Not implemented\n");
ret = -1;
} else if (ts->bus_type == HWIF_SPI) {
ret = touch_spi_xfer(to_spi_device(dev), xfer);
}
return ret;
}
static int rmi_spi_runtime_resume(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
struct rmi_spi_xport *rmi_spi = spi_get_drvdata(spi);
int ret;
enable_irq(rmi_spi->irq);
ret = rmi_driver_resume(rmi_spi->xport.rmi_dev);
if (ret)
dev_warn(dev, "Failed to resume device: %d\n", ret);
return 0;
}
/*
* NOTE: the suspend() method for an spi_master controller driver
* should verify that all its child devices are marked as suspended;
* suspend requests delivered through sysfs power/state files don't
* enforce such constraints.
*/
static int spi_suspend(struct device *dev, pm_message_t message)
{
int value;
struct spi_driver *drv = to_spi_driver(dev->driver);
if (!drv || !drv->suspend)
return 0;
/* suspend will stop irqs and dma; no more i/o */
value = drv->suspend(to_spi_device(dev), message);
if (value == 0)
dev->power.power_state = message;
return value;
}
static int spi_resume(struct device *dev)
{
int value;
struct spi_driver *drv = to_spi_driver(dev->driver);
if (!drv || !drv->resume)
return 0;
/* resume may restart the i/o queue */
value = drv->resume(to_spi_device(dev));
if (value == 0)
dev->power.power_state = PMSG_ON;
return value;
}
/**
* snd_soc_codec_set_cache_io: Set up standard I/O functions.
*
* @codec: CODEC to configure.
* @addr_bits: Number of bits of register address data.
* @data_bits: Number of bits of data per register.
* @control: Control bus used.
*
* Register formats are frequently shared between many I2C and SPI
* devices. In order to promote code reuse the ASoC core provides
* some standard implementations of CODEC read and write operations
* which can be set up using this function.
*
* The caller is responsible for allocating and initialising the
* actual cache.
*
* Note that at present this code cannot be used by CODECs with
* volatile registers.
*/
int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
int addr_bits, int data_bits,
enum snd_soc_control_type control)
{
struct regmap_config config;
int ret;
memset(&config, 0, sizeof(config));
codec->write = hw_write;
codec->read = hw_read;
config.reg_bits = addr_bits;
config.val_bits = data_bits;
switch (control) {
#if IS_ENABLED(CONFIG_REGMAP_I2C)
case SND_SOC_I2C:
codec->control_data = regmap_init_i2c(to_i2c_client(codec->dev),
&config);
break;
#endif
#if IS_ENABLED(CONFIG_REGMAP_SPI)
case SND_SOC_SPI:
codec->control_data = regmap_init_spi(to_spi_device(codec->dev),
&config);
break;
#endif
case SND_SOC_REGMAP:
/* Device has made its own regmap arrangements */
codec->using_regmap = true;
if (!codec->control_data)
codec->control_data = dev_get_regmap(codec->dev, NULL);
if (codec->control_data) {
ret = regmap_get_val_bytes(codec->control_data);
/* Errors are legitimate for non-integer byte
* multiples */
if (ret > 0)
codec->val_bytes = ret;
}
break;
default:
return -EINVAL;
}
return PTR_ERR_OR_ZERO(codec->control_data);
}
int snd_soc_codec_set_cache_io(struct snd_soc_codec *codec,
int addr_bits, int data_bits,
enum snd_soc_control_type control)
{
struct regmap_config config;
int ret;
memset(&config, 0, sizeof(config));
codec->write = hw_write;
codec->read = hw_read;
codec->bulk_write_raw = snd_soc_hw_bulk_write_raw;
config.reg_bits = addr_bits;
config.val_bits = data_bits;
switch (control) {
#if defined(CONFIG_REGMAP_I2C) || defined(CONFIG_REGMAP_I2C_MODULE)
case SND_SOC_I2C:
codec->control_data = regmap_init_i2c(to_i2c_client(codec->dev),
&config);
break;
#endif
#if defined(CONFIG_REGMAP_SPI) || defined(CONFIG_REGMAP_SPI_MODULE)
case SND_SOC_SPI:
codec->control_data = regmap_init_spi(to_spi_device(codec->dev),
&config);
break;
#endif
case SND_SOC_REGMAP:
codec->using_regmap = true;
ret = regmap_get_val_bytes(codec->control_data);
if (ret > 0)
codec->val_bytes = ret;
break;
default:
return -EINVAL;
}
if (IS_ERR(codec->control_data))
return PTR_ERR(codec->control_data);
return 0;
}
static int ssp_suspend(struct device *dev)
{
struct spi_device *spi_dev = to_spi_device(dev);
struct ssp_data *data = spi_get_drvdata(spi_dev);
func_dbg();
disable_debug_timer(data);
if (SUCCESS != ssp_send_cmd(data, MSG2SSP_AP_STATUS_SUSPEND, 0))
pr_err("[SSP]: %s MSG2SSP_AP_STATUS_SUSPEND failed\n",
__func__);
data->uLastResumeState = MSG2SSP_AP_STATUS_SUSPEND;
disable_irq(data->iIrq);
return 0;
}
static int ssp_resume(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
struct ssp_data *data = spi_get_drvdata(spi);
func_dbg();
enable_debug_timer(data);
if (SUCCESS != ssp_send_cmd(data, MSG2SSP_AP_STATUS_RESUME, 0))
pr_err("[SSP]: %s MSG2SSP_AP_STATUS_RESUME failed\n",
__func__);
data->uLastResumeState = MSG2SSP_AP_STATUS_RESUME;
return 0;
}
static int hts221_spi_read(struct device *dev, u8 addr, int len, u8 *data)
{
int err;
struct spi_device *spi = to_spi_device(dev);
struct iio_dev *iio_dev = spi_get_drvdata(spi);
struct hts221_hw *hw = iio_priv(iio_dev);
struct spi_transfer xfers[] = {
{
.tx_buf = hw->tb.tx_buf,
.bits_per_word = 8,
.len = 1,
},
{
.rx_buf = hw->tb.rx_buf,
static int max7301_spi_read(struct device *dev, unsigned int reg)
{
int ret;
u16 word;
struct spi_device *spi = to_spi_device(dev);
word = 0x8000 | (reg << 8);
ret = spi_write(spi, (const u8 *)&word, sizeof(word));
if (ret)
return ret;
ret = spi_read(spi, (u8 *)&word, sizeof(word));
if (ret)
return ret;
return word & 0xff;
}
static int
r2113s_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
struct r2113s_plat_data *pdata = spi->dev.platform_data;
u8 txbuf[5], rxbuf[7];
int ret;
/* Transfer 5 byte befores reading SEC. This gives 31us for carry. */
txbuf[0] = R2113S_CMD_R(R2113S_REG_CTL2); /* cmd, ctl2 */
txbuf[1] = 0xff; /* dummy */
txbuf[2] = R2113S_CMD_R(R2113S_REG_CTL2); /* cmd, ctl2 */
txbuf[3] = 0xff; /* dummy */
txbuf[4] = R2113S_CMD_MR(R2113S_REG_SECS); /* cmd, sec, ... */
memset(rxbuf,0xff,sizeof(rxbuf));
/* read in one transfer to avoid data inconsistency */
ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
rxbuf, sizeof(rxbuf));
udelay(62); /* Tcsr 62us */
if (ret < 0)
return ret;
tm->tm_sec = BCD2BIN(rxbuf[R2113S_REG_SECS] & R2113S_SECS_MASK);
tm->tm_min = BCD2BIN(rxbuf[R2113S_REG_MINS] & R2113S_MINS_MASK);
if (pdata->rtc_24h) {
tm->tm_hour = BCD2BIN(rxbuf[R2113S_REG_HOURS] & R2113S_HOURS_MASK);
} else {
tm->tm_hour = BCD2BIN((rxbuf[R2113S_REG_HOURS] & R2113S_HOURS_MASK)&~R2113S_BIT_PM);
tm->tm_hour %= 12;
if (rxbuf[R2113S_REG_HOURS] & R2113S_BIT_PM)
tm->tm_hour += 12;
}
tm->tm_wday = BCD2BIN(rxbuf[R2113S_REG_WDAY] & R2113S_WDAY_MASK);
tm->tm_mday = BCD2BIN(rxbuf[R2113S_REG_DAY] & R2113S_DAY_MASK);
tm->tm_mon =
BCD2BIN(rxbuf[R2113S_REG_MONTH] & R2113S_MONTH_MASK) - 1;
/* year is 1900 + tm->tm_year */
tm->tm_year = BCD2BIN(rxbuf[R2113S_REG_YEAR]) +
((rxbuf[R2113S_REG_MONTH] & R2113S_BIT_Y2K) ? 100 : 0);
if (rtc_valid_tm(tm) < 0) {
dev_err(&spi->dev, "retrieved date/time is not valid.\n");
rtc_time_to_tm(0, tm);
}
return 0;
}
static int
rs5c348_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
struct spi_device *spi = to_spi_device(dev);
struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
u8 txbuf[5], rxbuf[7];
int ret;
/* Transfer 5 byte befores reading SEC. This gives 31us for carry. */
txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
txbuf[1] = 0; /* dummy */
txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
txbuf[3] = 0; /* dummy */
txbuf[4] = RS5C348_CMD_MR(RS5C348_REG_SECS); /* cmd, sec, ... */
/* read in one transfer to avoid data inconsistency */
ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
rxbuf, sizeof(rxbuf));
udelay(62); /* Tcsr 62us */
if (ret < 0)
return ret;
tm->tm_sec = bcd2bin(rxbuf[RS5C348_REG_SECS] & RS5C348_SECS_MASK);
tm->tm_min = bcd2bin(rxbuf[RS5C348_REG_MINS] & RS5C348_MINS_MASK);
tm->tm_hour = bcd2bin(rxbuf[RS5C348_REG_HOURS] & RS5C348_HOURS_MASK);
if (!pdata->rtc_24h) {
if (rxbuf[RS5C348_REG_HOURS] & RS5C348_BIT_PM) {
tm->tm_hour -= 20;
tm->tm_hour %= 12;
tm->tm_hour += 12;
} else
tm->tm_hour %= 12;
}
tm->tm_wday = bcd2bin(rxbuf[RS5C348_REG_WDAY] & RS5C348_WDAY_MASK);
tm->tm_mday = bcd2bin(rxbuf[RS5C348_REG_DAY] & RS5C348_DAY_MASK);
tm->tm_mon =
bcd2bin(rxbuf[RS5C348_REG_MONTH] & RS5C348_MONTH_MASK) - 1;
/* year is 1900 + tm->tm_year */
tm->tm_year = bcd2bin(rxbuf[RS5C348_REG_YEAR]) +
((rxbuf[RS5C348_REG_MONTH] & RS5C348_BIT_Y2K) ? 100 : 0);
if (rtc_valid_tm(tm) < 0) {
dev_err(&spi->dev, "retrieved date/time is not valid.\n");
rtc_time_to_tm(0, tm);
}
return 0;
}
static ssize_t dac7512_store_val(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t count)
{
struct spi_device *spi = to_spi_device(dev);
unsigned char tmp[2];
unsigned long val;
if (strict_strtoul(buf, 10, &val) < 0)
return -EINVAL;
tmp[0] = val >> 8;
tmp[1] = val & 0xff;
spi_write(spi, tmp, sizeof(tmp));
return count;
}
static int ssp_resume(struct device *dev)
{
struct spi_device *spi_dev = to_spi_device(dev);
struct ssp_data *data = spi_get_drvdata(spi_dev);
enable_irq(data->iIrq);
ssp_infof();
enable_debug_timer(data);
if (SUCCESS != ssp_send_cmd(data, MSG2SSP_AP_STATUS_RESUME, 0))
ssp_errf("MSG2SSP_AP_STATUS_RESUME failed");
data->uLastResumeState = MSG2SSP_AP_STATUS_RESUME;
return 0;
}
static int ssp_suspend(struct device *dev)
{
struct spi_device *spi_dev = to_spi_device(dev);
struct ssp_data *data = spi_get_drvdata(spi_dev);
ssp_infof();
data->uLastResumeState = MSG2SSP_AP_STATUS_SUSPEND;
disable_debug_timer(data);
if (SUCCESS != ssp_send_cmd(data, MSG2SSP_AP_STATUS_SUSPEND, 0))
ssp_errf("MSG2SSP_AP_STATUS_SUSPEND failed");
data->bTimeSyncing = false;
disable_irq(data->iIrq);
return 0;
}
static int mcp795_rtcc_read(struct device *dev, u8 addr, u8 *buf, u8 count)
{
struct spi_device *spi = to_spi_device(dev);
int ret;
u8 tx[2];
tx[0] = MCP795_READ;
tx[1] = addr;
ret = spi_write_then_read(spi, tx, sizeof(tx), buf, count);
if (ret)
dev_err(dev, "Failed reading %d bytes from address %x.\n",
count, addr);
return ret;
}
static int read_regs(struct device *dev, unsigned char *regs, int no_regs)
{
struct spi_device *spi = to_spi_device(dev);
u8 txbuf[1], rxbuf[1];
int k, ret;
ret = 0;
for (k = 0; ret == 0 && k < no_regs; k++) {
txbuf[0] = 0x80 | regs[k];
ret = spi_write_then_read(spi, txbuf, 1, rxbuf, 1);
regs[k] = rxbuf[0];
}
return ret;
}
