/* use the larger of dc->emc_clk_rate or dc->new_emc_clk_rate, and copies * dc->new_emc_clk_rate into dc->emc_clk_rate. * calling this function both before and after a flip is sufficient to select * the best possible frequency and latency allowance. * set use_new to true to force dc->new_emc_clk_rate programming. */ void tegra_dc_program_bandwidth(struct tegra_dc *dc, bool use_new) { unsigned i; if (use_new || dc->emc_clk_rate != dc->new_emc_clk_rate) { /* going from 0 to non-zero */ if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk)) clk_prepare_enable(dc->emc_clk); clk_set_rate(dc->emc_clk, max(dc->emc_clk_rate, dc->new_emc_clk_rate)); dc->emc_clk_rate = dc->new_emc_clk_rate; /* going from non-zero to 0 */ if (!dc->new_emc_clk_rate && tegra_is_clk_enabled(dc->emc_clk)) clk_disable_unprepare(dc->emc_clk); } for (i = 0; i < DC_N_WINDOWS; i++) { struct tegra_dc_win *w = &dc->windows[i]; if ((use_new || w->bandwidth != w->new_bandwidth) && w->new_bandwidth != 0) tegra_dc_set_latency_allowance(dc, w); trace_program_bandwidth(dc); w->bandwidth = w->new_bandwidth; } }
/* use the larger of dc->emc_clk_rate or dc->new_emc_clk_rate, and copies * dc->new_emc_clk_rate into dc->emc_clk_rate. * calling this function both before and after a flip is sufficient to select * the best possible frequency and latency allowance. * set use_new to true to force dc->new_emc_clk_rate programming. */ void tegra_dc_program_bandwidth(struct tegra_dc *dc, bool use_new) { unsigned i; // // int temp_emc_clk; if (use_new || dc->emc_clk_rate != dc->new_emc_clk_rate) { /* going from 0 to non-zero */ if (!dc->emc_clk_rate && !tegra_is_clk_enabled(dc->emc_clk)) clk_enable(dc->emc_clk); // // clk_set_rate(dc->emc_clk, // max(dc->emc_clk_rate, dc->new_emc_clk_rate)); // // clk_set_rate(dc->emc_clk, max(dc->emc_clk_rate, dc->new_emc_clk_rate)); /* */ dc->emc_clk_rate = dc->new_emc_clk_rate; // // // // dc->emc_clk_rate = (dc->emc_clk_rate > 204000000) ? dc->emc_clk_rate : 204000000; //#endif // // /* going from non-zero to 0 */ if (!dc->new_emc_clk_rate && tegra_is_clk_enabled(dc->emc_clk)) clk_disable(dc->emc_clk); } /* */ for (i = 0; i < DC_N_WINDOWS; i++) { struct tegra_dc_win *w = &dc->windows[i]; if ((use_new || w->bandwidth != w->new_bandwidth) && w->new_bandwidth != 0) tegra_dc_set_latency_allowance(dc, w); trace_program_bandwidth(dc); w->bandwidth = w->new_bandwidth; } }