static void mt_debug_fiq(void *arg, void *regs, void *svc_sp) { u32 iir; int data = -1; int max_count = UART_FIFO_SIZE; unsigned int this_cpu; int need_irq = 1; iir = REG_UART_IIR; iir &= UART_IIR_INT_MASK; if (iir == UART_IIR_NO_INT_PENDING) return ; if (iir == UART_IIR_THRE) { } __push_event(iir, data); while (max_count-- > 0) { if (!(REG_UART_STATUS & 0x01)) { break; } if (is_fiq_debug_console_enable(arg)) { data = mt_console_uart->read_byte(mt_console_uart); if (data == FIQ_DEBUGGER_BREAK_CH) { /* enter FIQ debugger mode */ ret_FIQ_DEBUGGER_BREAK = 1; this_cpu = THREAD_INFO(svc_sp)->cpu; debug_handle_uart_interrupt(arg, this_cpu, regs, svc_sp); return ; } __push_event(UART_IIR_NO_INT_PENDING, data); /*why need_irq?*/ need_irq = 1; } else { this_cpu = THREAD_INFO(svc_sp)->cpu; need_irq = debug_handle_uart_interrupt(arg, this_cpu, regs, svc_sp); } } if (need_irq) { mt_disable_fiq(uart_irq_number); trigger_sw_irq(FIQ_DBG_SGI); } }
static void fiq_dbg_force_irq(struct platform_device *pdev, unsigned int irq) { trigger_sw_irq(irq); }