bool
aarch_rev16_shleft_mask_imm_p (rtx val, enum machine_mode mode)
{
return CONST_INT_P (val)
&& INTVAL (val)
== trunc_int_for_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff00),
mode);
}
static void
expand_one_stack_var_at (tree decl, HOST_WIDE_INT offset)
{
HOST_WIDE_INT align;
rtx x;
/* If this fails, we've overflowed the stack frame. Error nicely? */
gcc_assert (offset == trunc_int_for_mode (offset, Pmode));
x = plus_constant (virtual_stack_vars_rtx, offset);
x = gen_rtx_MEM (DECL_MODE (decl), x);
/* Set alignment we actually gave this decl. */
offset -= frame_phase;
align = offset & -offset;
align *= BITS_PER_UNIT;
if (align > STACK_BOUNDARY || align == 0)
align = STACK_BOUNDARY;
DECL_ALIGN (decl) = align;
DECL_USER_ALIGN (decl) = 0;
set_mem_attributes (x, decl, true);
SET_DECL_RTL (decl, x);
}
static inline int
x86_64_zext_immediate_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
#line 221 "../.././gcc/config/i386/predicates.md"
{
switch (GET_CODE (op))
{
case CONST_DOUBLE:
if (HOST_BITS_PER_WIDE_INT == 32)
return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
else
return 0;
case CONST_INT:
if (HOST_BITS_PER_WIDE_INT == 32)
return INTVAL (op) >= 0;
else
return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
case SYMBOL_REF:
/* For certain code models, the symbolic references are known to fit. */
/* TLS symbols are not constant. */
if (SYMBOL_REF_TLS_MODEL (op))
return false;
return (ix86_cmodel == CM_SMALL
|| (ix86_cmodel == CM_MEDIUM
&& !SYMBOL_REF_FAR_ADDR_P (op)));
case LABEL_REF:
/* For certain code models, the code is near as well. */
return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
case CONST:
/* We also may accept the offsetted memory references in certain
special cases. */
if (GET_CODE (XEXP (op, 0)) == PLUS)
{
rtx op1 = XEXP (XEXP (op, 0), 0);
rtx op2 = XEXP (XEXP (op, 0), 1);
if (ix86_cmodel == CM_LARGE)
return 0;
switch (GET_CODE (op1))
{
case SYMBOL_REF:
/* TLS symbols are not constant. */
if (SYMBOL_REF_TLS_MODEL (op1))
return 0;
/* For small code model we may accept pretty large positive
offsets, since one bit is available for free. Negative
offsets are limited by the size of NULL pointer area
specified by the ABI. */
if ((ix86_cmodel == CM_SMALL
|| (ix86_cmodel == CM_MEDIUM
&& !SYMBOL_REF_FAR_ADDR_P (op1)))
&& CONST_INT_P (op2)
&& trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
&& trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
return 1;
/* ??? For the kernel, we may accept adjustment of
-0x10000000, since we know that it will just convert
negative address space to positive, but perhaps this
is not worthwhile. */
break;
case LABEL_REF:
/* These conditions are similar to SYMBOL_REF ones, just the
constraints for code models differ. */
if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
&& CONST_INT_P (op2)
&& trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
&& trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
return 1;
break;
default:
return 0;
}
}
break;
default:
gcc_unreachable ();
}
return 0;
}
static inline int
x86_64_immediate_operand_1 (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
#line 94 "../.././gcc/config/i386/predicates.md"
{
if (!TARGET_64BIT)
return immediate_operand (op, mode);
switch (GET_CODE (op))
{
case CONST_INT:
/* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
to be at least 32 and this all acceptable constants are
represented as CONST_INT. */
if (HOST_BITS_PER_WIDE_INT == 32)
return 1;
else
{
HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
return trunc_int_for_mode (val, SImode) == val;
}
break;
case SYMBOL_REF:
/* For certain code models, the symbolic references are known to fit.
in CM_SMALL_PIC model we know it fits if it is local to the shared
library. Don't count TLS SYMBOL_REFs here, since they should fit
only if inside of UNSPEC handled below. */
/* TLS symbols are not constant. */
if (SYMBOL_REF_TLS_MODEL (op))
return false;
return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
|| (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
case LABEL_REF:
/* For certain code models, the code is near as well. */
return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
|| ix86_cmodel == CM_KERNEL);
case CONST:
/* We also may accept the offsetted memory references in certain
special cases. */
if (GET_CODE (XEXP (op, 0)) == UNSPEC)
switch (XINT (XEXP (op, 0), 1))
{
case UNSPEC_GOTPCREL:
case UNSPEC_DTPOFF:
case UNSPEC_GOTNTPOFF:
case UNSPEC_NTPOFF:
return 1;
default:
break;
}
if (GET_CODE (XEXP (op, 0)) == PLUS)
{
rtx op1 = XEXP (XEXP (op, 0), 0);
rtx op2 = XEXP (XEXP (op, 0), 1);
HOST_WIDE_INT offset;
if (ix86_cmodel == CM_LARGE)
return 0;
if (!CONST_INT_P (op2))
return 0;
offset = trunc_int_for_mode (INTVAL (op2), DImode);
switch (GET_CODE (op1))
{
case SYMBOL_REF:
/* TLS symbols are not constant. */
if (SYMBOL_REF_TLS_MODEL (op1))
return 0;
/* For CM_SMALL assume that latest object is 16MB before
end of 31bits boundary. We may also accept pretty
large negative constants knowing that all objects are
in the positive half of address space. */
if ((ix86_cmodel == CM_SMALL
|| (ix86_cmodel == CM_MEDIUM
&& !SYMBOL_REF_FAR_ADDR_P (op1)))
&& offset < 16*1024*1024
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
/* For CM_KERNEL we know that all object resist in the
negative half of 32bits address space. We may not
accept negative offsets, since they may be just off
and we may accept pretty large positive ones. */
if (ix86_cmodel == CM_KERNEL
&& offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
break;
case LABEL_REF:
/* These conditions are similar to SYMBOL_REF ones, just the
constraints for code models differ. */
if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
&& offset < 16*1024*1024
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
if (ix86_cmodel == CM_KERNEL
&& offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
break;
case UNSPEC:
switch (XINT (op1, 1))
{
case UNSPEC_DTPOFF:
case UNSPEC_NTPOFF:
if (offset > 0
&& trunc_int_for_mode (offset, SImode) == offset)
return 1;
}
break;
default:
break;
}
}
break;
default:
gcc_unreachable ();
}
return 0;
}
void
eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
HOST_WIDE_INT update_sp_offset)
{
int icode = recog_memoized (insn);
rtx old_set = single_set (insn);
bool validate_p;
int i;
rtx substed_operand[MAX_RECOG_OPERANDS];
rtx orig_operand[MAX_RECOG_OPERANDS];
struct lra_elim_table *ep;
rtx plus_src, plus_cst_src;
lra_insn_recog_data_t id;
struct lra_static_insn_data *static_id;
if (icode < 0 && asm_noperands (PATTERN (insn)) < 0 && ! DEBUG_INSN_P (insn))
{
lra_assert (GET_CODE (PATTERN (insn)) == USE
|| GET_CODE (PATTERN (insn)) == CLOBBER
|| GET_CODE (PATTERN (insn)) == ASM_INPUT);
return;
}
/* Check for setting an eliminable register. */
if (old_set != 0 && REG_P (SET_DEST (old_set))
&& (ep = get_elimination (SET_DEST (old_set))) != NULL)
{
for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
{
bool delete_p = replace_p;
#ifdef HARD_FRAME_POINTER_REGNUM
if (ep->from == FRAME_POINTER_REGNUM
&& ep->to == HARD_FRAME_POINTER_REGNUM)
/* If this is setting the frame pointer register to the
hardware frame pointer register and this is an
elimination that will be done (tested above), this
insn is really adjusting the frame pointer downward
to compensate for the adjustment done before a
nonlocal goto. */
{
rtx src = SET_SRC (old_set);
rtx off = remove_reg_equal_offset_note (insn, ep->to_rtx);
/* We should never process such insn with non-zero
UPDATE_SP_OFFSET. */
lra_assert (update_sp_offset == 0);
if (off != NULL_RTX
|| src == ep->to_rtx
|| (GET_CODE (src) == PLUS
&& XEXP (src, 0) == ep->to_rtx
&& CONST_INT_P (XEXP (src, 1))))
{
HOST_WIDE_INT offset;
if (replace_p)
{
SET_DEST (old_set) = ep->to_rtx;
lra_update_insn_recog_data (insn);
return;
}
offset = (off != NULL_RTX ? INTVAL (off)
: src == ep->to_rtx ? 0 : INTVAL (XEXP (src, 1)));
offset -= (ep->offset - ep->previous_offset);
src = plus_constant (Pmode, ep->to_rtx, offset);
/* First see if this insn remains valid when we
make the change. If not, keep the INSN_CODE
the same and let the constraint pass fit it
up. */
validate_change (insn, &SET_SRC (old_set), src, 1);
validate_change (insn, &SET_DEST (old_set),
ep->from_rtx, 1);
if (! apply_change_group ())
{
SET_SRC (old_set) = src;
SET_DEST (old_set) = ep->from_rtx;
}
lra_update_insn_recog_data (insn);
/* Add offset note for future updates. */
add_reg_note (insn, REG_EQUAL, src);
return;
}
}
#endif
/* This insn isn't serving a useful purpose. We delete it
when REPLACE is set. */
if (delete_p)
lra_delete_dead_insn (insn);
return;
}
}
/* We allow one special case which happens to work on all machines we
currently support: a single set with the source or a REG_EQUAL
note being a PLUS of an eliminable register and a constant. */
plus_src = plus_cst_src = 0;
if (old_set && REG_P (SET_DEST (old_set)))
{
if (GET_CODE (SET_SRC (old_set)) == PLUS)
plus_src = SET_SRC (old_set);
/* First see if the source is of the form (plus (...) CST). */
if (plus_src
&& CONST_INT_P (XEXP (plus_src, 1)))
plus_cst_src = plus_src;
/* Check that the first operand of the PLUS is a hard reg or
the lowpart subreg of one. */
if (plus_cst_src)
{
rtx reg = XEXP (plus_cst_src, 0);
if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
plus_cst_src = 0;
}
}
if (plus_cst_src)
{
rtx reg = XEXP (plus_cst_src, 0);
HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
if (REG_P (reg) && (ep = get_elimination (reg)) != NULL)
{
rtx to_rtx = replace_p ? ep->to_rtx : ep->from_rtx;
if (! replace_p)
{
if (update_sp_offset == 0)
offset += (ep->offset - ep->previous_offset);
if (ep->to_rtx == stack_pointer_rtx)
{
if (first_p)
offset -= lra_get_insn_recog_data (insn)->sp_offset;
else
offset += update_sp_offset;
}
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
}
if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), to_rtx);
/* If we have a nonzero offset, and the source is already a
simple REG, the following transformation would increase
the cost of the insn by replacing a simple REG with (plus
(reg sp) CST). So try only when we already had a PLUS
before. */
if (offset == 0 || plus_src)
{
rtx new_src = plus_constant (GET_MODE (to_rtx), to_rtx, offset);
old_set = single_set (insn);
/* First see if this insn remains valid when we make the
change. If not, try to replace the whole pattern
with a simple set (this may help if the original insn
was a PARALLEL that was only recognized as single_set
due to REG_UNUSED notes). If this isn't valid
either, keep the INSN_CODE the same and let the
constraint pass fix it up. */
if (! validate_change (insn, &SET_SRC (old_set), new_src, 0))
{
rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src);
if (! validate_change (insn, &PATTERN (insn), new_pat, 0))
SET_SRC (old_set) = new_src;
}
lra_update_insn_recog_data (insn);
/* This can't have an effect on elimination offsets, so skip
right to the end. */
return;
}
}
}
/* Eliminate all eliminable registers occurring in operands that
can be handled by the constraint pass. */
id = lra_get_insn_recog_data (insn);
static_id = id->insn_static_data;
validate_p = false;
for (i = 0; i < static_id->n_operands; i++)
{
orig_operand[i] = *id->operand_loc[i];
substed_operand[i] = *id->operand_loc[i];
/* For an asm statement, every operand is eliminable. */
if (icode < 0 || insn_data[icode].operand[i].eliminable)
{
/* Check for setting a hard register that we know about. */
if (static_id->operand[i].type != OP_IN
&& REG_P (orig_operand[i]))
{
/* If we are assigning to a hard register that can be
eliminated, it must be as part of a PARALLEL, since
the code above handles single SETs. This reg can not
be longer eliminated -- it is forced by
mark_not_eliminable. */
for (ep = reg_eliminate;
ep < ®_eliminate[NUM_ELIMINABLE_REGS];
ep++)
lra_assert (ep->from_rtx != orig_operand[i]
|| ! ep->can_eliminate);
}
/* Companion to the above plus substitution, we can allow
invariants as the source of a plain move. */
substed_operand[i]
= lra_eliminate_regs_1 (insn, *id->operand_loc[i], VOIDmode,
replace_p, ! replace_p && ! first_p,
update_sp_offset, first_p);
if (substed_operand[i] != orig_operand[i])
validate_p = true;
}
}
if (! validate_p)
return;
/* Substitute the operands; the new values are in the substed_operand
array. */
for (i = 0; i < static_id->n_operands; i++)
*id->operand_loc[i] = substed_operand[i];
for (i = 0; i < static_id->n_dups; i++)
*id->dup_loc[i] = substed_operand[(int) static_id->dup_num[i]];
/* If we had a move insn but now we don't, re-recognize it.
This will cause spurious re-recognition if the old move had a
PARALLEL since the new one still will, but we can't call
single_set without having put new body into the insn and the
re-recognition won't hurt in this rare case. */
id = lra_update_insn_recog_data (insn);
static_id = id->insn_static_data;
}
static int
reload_cse_simplify_set (rtx set, rtx insn)
{
int did_change = 0;
int dreg;
rtx src;
enum reg_class dclass;
int old_cost;
cselib_val *val;
struct elt_loc_list *l;
#ifdef LOAD_EXTEND_OP
enum rtx_code extend_op = UNKNOWN;
#endif
bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn));
dreg = true_regnum (SET_DEST (set));
if (dreg < 0)
return 0;
src = SET_SRC (set);
if (side_effects_p (src) || true_regnum (src) >= 0)
return 0;
dclass = REGNO_REG_CLASS (dreg);
#ifdef LOAD_EXTEND_OP
/* When replacing a memory with a register, we need to honor assumptions
that combine made wrt the contents of sign bits. We'll do this by
generating an extend instruction instead of a reg->reg copy. Thus
the destination must be a register that we can widen. */
if (MEM_P (src)
&& GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
&& (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != UNKNOWN
&& !REG_P (SET_DEST (set)))
return 0;
#endif
val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
if (! val)
return 0;
/* If memory loads are cheaper than register copies, don't change them. */
if (MEM_P (src))
old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
else if (REG_P (src))
old_cost = REGISTER_MOVE_COST (GET_MODE (src),
REGNO_REG_CLASS (REGNO (src)), dclass);
else
old_cost = rtx_cost (src, SET, speed);
for (l = val->locs; l; l = l->next)
{
rtx this_rtx = l->loc;
int this_cost;
if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
{
#ifdef LOAD_EXTEND_OP
if (extend_op != UNKNOWN)
{
HOST_WIDE_INT this_val;
/* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
constants, such as SYMBOL_REF, cannot be extended. */
if (GET_CODE (this_rtx) != CONST_INT)
continue;
this_val = INTVAL (this_rtx);
switch (extend_op)
{
case ZERO_EXTEND:
this_val &= GET_MODE_MASK (GET_MODE (src));
break;
case SIGN_EXTEND:
/* ??? In theory we're already extended. */
if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
break;
default:
gcc_unreachable ();
}
this_rtx = GEN_INT (this_val);
}
#endif
this_cost = rtx_cost (this_rtx, SET, speed);
}
else if (REG_P (this_rtx))
{
#ifdef LOAD_EXTEND_OP
if (extend_op != UNKNOWN)
{
this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
this_cost = rtx_cost (this_rtx, SET, speed);
}
else
#endif
this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
REGNO_REG_CLASS (REGNO (this_rtx)),
dclass);
}
else
continue;
/* If equal costs, prefer registers over anything else. That
tends to lead to smaller instructions on some machines. */
if (this_cost < old_cost
|| (this_cost == old_cost
&& REG_P (this_rtx)
&& !REG_P (SET_SRC (set))))
{
#ifdef LOAD_EXTEND_OP
if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
&& extend_op != UNKNOWN
#ifdef CANNOT_CHANGE_MODE_CLASS
&& !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)),
word_mode,
REGNO_REG_CLASS (REGNO (SET_DEST (set))))
#endif
)
{
rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
validate_change (insn, &SET_DEST (set), wide_dest, 1);
}
#endif
validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1);
old_cost = this_cost, did_change = 1;
}
}
return did_change;
}