void signing_init(uint32_t _inputs_count, uint32_t _outputs_count, const CoinType *_coin, const HDNode *_root)
{
inputs_count = _inputs_count;
outputs_count = _outputs_count;
coin = _coin;
root = _root;
idx1 = 0;
to_spend = 0;
spending = 0;
change_spend = 0;
memset(&input, 0, sizeof(TxInputType));
memset(&resp, 0, sizeof(TxRequest));
signing = true;
multisig_fp_set = false;
multisig_fp_mismatch = false;
tx_init(&to, inputs_count, outputs_count, version, lock_time, false);
sha256_Init(&tc);
sha256_Update(&tc, (const uint8_t *)&inputs_count, sizeof(inputs_count));
sha256_Update(&tc, (const uint8_t *)&outputs_count, sizeof(outputs_count));
sha256_Update(&tc, (const uint8_t *)&version, sizeof(version));
sha256_Update(&tc, (const uint8_t *)&lock_time, sizeof(lock_time));
raw_tx_status = NOT_PARSING;
send_req_1_input();
}
int inittx_ref(tx_ref_t *ref, tx_t *tx, char *name, char *hash, int type)
{
shkey_t *tx_key;
int err;
memset(ref->ref.ref_name, 0, sizeof(ref->ref.ref_name));
memset(ref->ref.ref_hash, 0, sizeof(ref->ref.ref_hash));
/* attributes */
if (name)
strncpy(ref->ref.ref_name, name, sizeof(ref->ref.ref_name)-1);
if (hash)
strncpy(ref->ref.ref_hash, hash, sizeof(ref->ref.ref_hash)-1);
ref->ref.ref_type = type;
ref->ref.ref_level = tx->tx_op;
/* origin peer */
memcpy(&ref->ref.ref_peer, &tx->tx_peer, sizeof(ref->ref.ref_peer));
/* populate unique key into 'external hash reference' if none specified. */
if (!*ref->ref.ref_hash) {
tx_key = get_tx_key(tx);
if (tx_key)
memcpy(&ref->ref.ref_hash, shkey_print(tx_key), sizeof(ref->ref.ref_hash));
}
/* generate new reference */
err = tx_init(NULL, (tx_t *)ref, TX_REFERENCE);
if (err)
return (err);
return (0);
}
int create_bond_asset(shkey_t *id_key, tx_bond_t *bond, size_t bond_nr, tx_asset_t **asset_p)
{
tx_asset_t *asset;
shpeer_t *peer;
size_t len;
int err;
peer = load_asset_peer(id_key);
if (!peer)
return (SHERR_INVAL);
len = sizeof(tx_asset_t) + (sizeof(tx_bond_t) * bond_nr);
asset = (tx_asset_t *)calloc(len, sizeof(char));
if (!asset)
return (SHERR_NOMEM);
asset->ass.ass_birth = shtime();
asset->ass_type = TX_BOND;
/* asset content */
asset->ass_size = (sizeof(tx_bond_t) * bond_nr);
memcpy((unsigned char *)asset->ass_data,
(unsigned char *)bond, (sizeof(tx_bond_t) * bond_nr));
/* generate signature based on identity's priveleged key */
memcpy(&asset->ass.ass_id, id_key, sizeof(asset->ass.ass_id));
generate_asset_signature(asset, peer);
err = tx_init(NULL, (tx_t *)asset, TX_ASSET);
if (err)
return (err);
return (0);
}
void open_channel(unsigned long long pci_mem_addr)
{
int fd;
void *ptr;
if(!pci_mem_addr){
if ((fd = shm_open("channel", O_CREAT|O_RDWR,
S_IRWXU|S_IRWXG|S_IRWXO)) > 0) {
if (ftruncate(fd, 1024) != 0)
DIE("could not truncate shared file\n");
}
else
DIE("Open channel");
ptr = mmap(NULL,1024,PROT_READ|PROT_WRITE,MAP_SHARED,fd,0);
if(ptr == MAP_FAILED)
DIE("mmap");
}
else{
fprintf(stderr,"Using provide address cookie 0x%llx\n",pci_mem_addr);
fd = open ( "/dev/mem", O_RDWR);
ptr = mmap(NULL, 1024, PROT_READ|PROT_WRITE, MAP_SHARED, fd, (off_t)pci_mem_addr);
if (!ptr) {
printf("Cannot map 0x%llx with size of %x\n", pci_mem_addr, 1024);
exit(0);
}
}
spinlock = ptr; /* spinlock is the first object in the mmap */
if(transmitter)
tx_init();
else
rx_init();
return;
}
int inittx_ward(tx_ward_t *ward, tx_t *tx, tx_context_t *ctx)
{
shkey_t *tx_key;
int err;
tx_key = get_tx_key(tx);
if (!tx_key)
return (SHERR_INVAL);
memcpy(&ward->ward_ref, tx_key, sizeof(ward->ward_ref));
txward_context_sign(ward, ctx);
err = tx_init(NULL, (tx_t *)ward, TX_WARD);
if (err)
return (err);
return (0);
}
int inittx_contract(tx_contract_t *con, char *type, char *name, char *key)
{
int err;
if (!type || !name || !key)
return (SHERR_INVAL);
memset(con->con_cur, 0, sizeof(con->con_cur));
memset(con->con_name, 0, sizeof(con->con_name));
memset(con->con_key, 0, sizeof(con->con_key));
strncpy(con->con_cur, type, sizeof(con->con_cur)-1);
strncpy(con->con_name, name, sizeof(con->con_name)-1);
strncpy(con->con_key, key, sizeof(con->con_key)-1);
err = tx_init(NULL, (tx_t *)con, TX_WALLET);
if (err)
return (err);
return (0);
}
int
main (void)
{
SystemInit ();
debug_init ();
#ifdef DEBUG_LEVEL
debug_set_level (DEBUG_LEVEL);
#endif
DBG_NEWLINE (DBG_LEVEL_INFO);
DBG (DBG_LEVEL_INFO, "HAM relay firmware v" VERSION_STR " (" __GIT_SHA1__ ")");
DBG (DBG_LEVEL_INFO, "Compiled " __DATE__ " at " __TIME__ " on " __BUILD_HOSTNAME__ " using GCC " __VERSION__ " (%d.%d-%d)", __CS_SOURCERYGXX_MAJ__, __CS_SOURCERYGXX_MIN__, __CS_SOURCERYGXX_REV__);
DBG (DBG_LEVEL_INFO, "MCU running at %d MHz", SystemCoreClock / 1000000);
inputs_init ();
systick_init ();
tx_init ();
tone_init ();
roger_beep_init ();
call_init ();
call_transmit_delay (5);
while (1) {
if (!tx_is_enabled ()) {
roger_beep_transmit_if_needed ();
call_transmit_if_needed ();
}
__WFI ();
}
return 0;
}
int inittx_trust(tx_trust_t *trust, tx_t *ref_tx, shkey_t *context)
{
shkey_t *tx_key;
int err;
if (!trust)
return (SHERR_INVAL);
tx_key = get_tx_key(ref_tx);
if (!tx_key)
return (SHERR_INVAL);
if (!context)
context = ashkey_blank();
memcpy(&trust->trust_ref, tx_key, sizeof(shkey_t));
memcpy(&trust->trust_ctx, context, sizeof(shkey_t));
err = tx_init(NULL, trust, TX_TRUST);
if (err)
return (err);
return (0);
}
/**
* Creates a new bond with the local shared as sender.
* @note Set the bond state to confirm to initiate transaction.
*/
tx_bond_t *create_bond(shkey_t *bond_key, double duration, double fee, double basis)
{
bond = (tx_bond_t *)calloc(1, sizeof(tx_bond_t));
if (!bond)
return (SHERR_NOMEM);
local_transid_generate(TX_BOND, &bond->tx);
bond->bond_stamp = shtime64();
bond->bond_stamp = shtime_adj(bond->bond_stamp, duration);
bond->bond_credit = (uint64_t)(fee / 0.00000001);
bond->bond_basis = (uint32_t)(basis * 10000);
bond->bond_state = TXBOND_PENDING;
/* authenticate bond info */
generate_bond_signature(bond);
err = tx_init(NULL, (tx_t *)bond, TX_BOND);
if (err)
return (err);
return (bond);
}
int
main(void)
{
wdt_disable();
// un-reset ethernet
ENC28J60_RESET_DDR |= _BV( ENC28J60_RESET_BIT );
ENC28J60_RESET_PORT |= _BV( ENC28J60_RESET_BIT );
led_init();
LED_ON();
spi_init();
eeprom_init();
// if we had been restarted by watchdog check the REQ BootLoader byte in the
// EEPROM ...
if(bit_is_set(MCUSR,WDRF) && eeprom_read_byte(EE_REQBL)) {
eeprom_write_byte( EE_REQBL, 0 ); // clear flag
// TBD: This is useless as button needs to be pressed - needs moving into bootloader directly
// start_bootloader();
}
// Setup OneWire and make a full search at the beginning (takes some time)
#ifdef HAS_ONEWIRE
i2c_init();
onewire_Init();
onewire_FullSearch();
#endif
// Setup the timers. Are needed for watchdog-reset
#if defined (HAS_IRRX) || defined (HAS_IRTX)
ir_init();
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel = (DISPLAY_USB|DISPLAY_RFROUTER);
#else
display_channel = DISPLAY_USB;
#endif
ethernet_init();
LED_OFF();
sei();
for(;;) {
uart_task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_IRRX
ir_task();
#endif
#ifdef HAS_ETHERNET
Ethernet_Task();
#endif
}
}
int
main(void)
{
wdt_disable();
#ifdef CSMV4
LED_ON_DDR |= _BV( LED_ON_PIN );
LED_ON_PORT |= _BV( LED_ON_PIN );
#endif
led_init();
LED_ON();
spi_init();
// eeprom_factory_reset("xx");
eeprom_init();
// led_mode = 2;
// if we had been restarted by watchdog check the REQ BootLoader byte in the
// EEPROM ...
// if(bit_is_set(MCUSR,WDRF) && eeprom_read_byte(EE_REQBL)) {
// eeprom_write_byte( EE_REQBL, 0 ); // clear flag
// start_bootloader();
// }
// Setup the timers. Are needed for watchdog-reset
#ifdef HAS_IRRX
ir_init();
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
#ifdef HAS_DOGM
dogm_init();
#endif
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
display_channel = DISPLAY_USB;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel |= DISPLAY_RFROUTER;
#endif
#ifdef HAS_DOGM
display_channel |= DISPLAY_DOGM;
#endif
LED_OFF();
sei();
for(;;) {
uart_task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_IRRX
ir_task();
#endif
}
}
int
main(void)
{
wdt_disable();
clock_prescale_set(clock_div_1);
LED_ON_DDR |= _BV( LED_ON_PIN );
LED_ON_PORT |= _BV( LED_ON_PIN );
led_init();
LED_ON();
spi_init();
// eeprom_factory_reset("xx");
eeprom_init();
// Setup OneWire and make a full search at the beginning (takes some time)
#ifdef HAS_ONEWIRE
i2c_init();
onewire_Init();
onewire_FullSearch();
#endif
// Setup the timers. Are needed for watchdog-reset
#if defined (HAS_IRRX) || defined (HAS_IRTX)
ir_init();
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz
#else
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
display_channel = DISPLAY_USB;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel |= DISPLAY_RFROUTER;
#endif
checkFrequency();
LED_OFF();
sei();
for(;;) {
uart_task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_RWE
rf_rwe_task();
#endif
#if defined(HAS_IRRX) || defined(HAS_IRTX)
ir_task();
#endif
#ifdef HAS_MBUS
rf_mbus_task();
#endif
}
}
int main(int argc,char* argv[]) {
struct dspserver_config config;
memset(&config, 0, sizeof(config));
// Register signal and signal handler
signal(SIGINT, signal_shutdown);
char directory[MAXPATHLEN];
strcpy(config.soundCardName,"HPSDR");
strcpy(config.server_address,"127.0.0.1"); // localhost
strcpy(config.share_config_file, getenv("HOME"));
strcat(config.share_config_file, "/dspserver.conf");
processCommands(argc,argv,&config);
fprintf(stderr, "Reading conf file %s\n", config.share_config_file);
init_register(config.share_config_file); // we now read our conf always
// start web registration if set
if (toShareOrNotToShare) {
fprintf(stderr, "Activating Web register\n");
}
fprintf(stderr,"gHPSDR rx %d (Version %s)\n",receiver,VERSION);
printversion();
setSoundcard(getSoundcardId(config.soundCardName));
// initialize DttSP
if(getcwd(directory, sizeof(directory))==NULL) {
fprintf(stderr,"current working directory path is > MAXPATHLEN");
exit(1);
}
Setup_SDR(directory);
Release_Update();
SetTRX(0,0); // thread 0 is for receive
SetTRX(1,1); // thread 1 is for transmit
SetRingBufferOffset(0,config.offset);
SetThreadProcessingMode(0,RUN_PLAY);
SetThreadProcessingMode(1,RUN_PLAY);
SetSubRXSt(0,1,1);
SetRXOutputGain(0,0,0.20);
SetRXOsc(0,0, -LO_offset);
SetRXOsc(0,1, -LO_offset);
reset_for_buflen(0,1024);
reset_for_buflen(1,1024);
client_init(receiver);
audio_stream_init(receiver);
audio_stream_reset();
codec2 = codec2_create();
G711A_init();
ozy_init(config.server_address);
SetMode(1, 0, USB);
SetTXFilter(1, 150, 2850);
SetTXOsc(1, LO_offset);
SetTXAMCarrierLevel(1, 0.5);
tx_init(); // starts the tx_thread
while(1) {
sleep(10000);
}
// codec2_destroy(codec2);
return 0;
}
//------------------------------------------------------------------------------
/// Application entry point. Configures the DBGU, PIT, TC0, LEDs and buttons
/// and makes LED\#1 blink in its infinite loop, using the Wait function.
/// \return Unused (ANSI-C compatibility).
//------------------------------------------------------------------------------
int main(void)
{
// DBGU configuration
TRACE_CONFIGURE(DBGU_STANDARD, 115200, BOARD_MCK);
TRACE_INFO_WP("\n\r");
TRACE_INFO("Getting new Started Project --\n\r");
TRACE_INFO("%s\n\r", BOARD_NAME);
TRACE_INFO("Compiled: %s %s --\n\r", __DATE__, __TIME__);
//Configure Reset Controller
AT91C_BASE_RSTC->RSTC_RMR= 0xa5<<24;
// Configure EMAC PINS
PIO_Configure(emacRstPins, PIO_LISTSIZE(emacRstPins));
// Execute reset
RSTC_SetExtResetLength(0xd);
RSTC_ExtReset();
// Wait for end hardware reset
while (!RSTC_GetNrstLevel());
TRACE_INFO("init Flash\n\r");
flash_init();
TRACE_INFO("init Timer\n\r");
// Configure timer 0
ticks=0;
extern void ISR_Timer0();
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0);
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
AT91C_BASE_TC0->TC_IDR = 0xFFFFFFFF;
AT91C_BASE_TC0->TC_SR;
AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV5_CLOCK | AT91C_TC_CPCTRG;
AT91C_BASE_TC0->TC_RC = 375;
AT91C_BASE_TC0->TC_IER = AT91C_TC_CPCS;
AIC_ConfigureIT(AT91C_ID_TC0, AT91C_AIC_PRIOR_LOWEST, ISR_Timer0);
AIC_EnableIT(AT91C_ID_TC0);
AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
// Configure timer 1
extern void ISR_Timer1();
AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);
AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; //Stop clock
AT91C_BASE_TC1->TC_IDR = 0xFFFFFFFF; //Disable Interrupts
AT91C_BASE_TC1->TC_SR; //Read Status register
AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV4_CLOCK | AT91C_TC_CPCTRG; // Timer1: 2,666us = 48MHz/128
AT91C_BASE_TC1->TC_RC = 0xffff;
AT91C_BASE_TC1->TC_IER = AT91C_TC_CPCS;
AIC_ConfigureIT(AT91C_ID_TC1, 1, ISR_Timer1);
AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
led_init();
TRACE_INFO("init EEprom\n\r");
eeprom_init();
rb_reset(&TTY_Rx_Buffer);
rb_reset(&TTY_Tx_Buffer);
input_handle_func = analyze_ttydata;
LED_OFF();
LED2_OFF();
LED3_OFF();
spi_init();
fht_init();
tx_init();
#ifdef HAS_ETHERNET
ethernet_init();
#endif
TRACE_INFO("init USB\n\r");
CDCDSerialDriver_Initialize();
USBD_Connect();
wdt_enable(WDTO_2S);
fastrf_on=0;
display_channel = DISPLAY_USB;
TRACE_INFO("init Complete\n\r");
checkFrequency();
// Main loop
while (1) {
CDC_Task();
Minute_Task();
RfAnalyze_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_RWE
rf_rwe_task();
#endif
#ifdef HAS_MBUS
rf_mbus_task();
#endif
#ifdef HAS_MAICO
rf_maico_task();
#endif
#ifdef HAS_ETHERNET
Ethernet_Task();
#endif
#ifdef DBGU_UNIT_IN
if(DBGU_IsRxReady()){
unsigned char volatile * const ram = (unsigned char *) AT91C_ISRAM;
unsigned char x;
x=DBGU_GetChar();
switch(x) {
case 'd':
puts("USB disconnect\n\r");
USBD_Disconnect();
break;
case 'c':
USBD_Connect();
puts("USB Connect\n\r");
break;
case 'r':
//Configure Reset Controller
AT91C_BASE_RSTC->RSTC_RMR=AT91C_RSTC_URSTEN | 0xa5<<24;
break;
case 'S':
USBD_Disconnect();
my_delay_ms(250);
my_delay_ms(250);
//Reset
*ram = 0xaa;
AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST | AT91C_RSTC_EXTRST | 0xA5<<24;
while (1);
break;
default:
rb_put(&TTY_Tx_Buffer, x);
}
}
#endif
if (USBD_GetState() == USBD_STATE_CONFIGURED) {
if( USBState == STATE_IDLE ) {
CDCDSerialDriver_Read(usbBuffer,
DATABUFFERSIZE,
(TransferCallback) UsbDataReceived,
0);
LED3_ON();
USBState=STATE_RX;
}
}
if( USBState == STATE_SUSPEND ) {
TRACE_INFO("suspend !\n\r");
USBState = STATE_IDLE;
}
if( USBState == STATE_RESUME ) {
TRACE_INFO("resume !\n\r");
USBState = STATE_IDLE;
}
}
}
int main(int argc,char* argv[]) {
memset(&config, 0, sizeof(config));
// Register signal and signal handler
signal(SIGINT, signal_shutdown);
char directory[MAXPATHLEN];
strcpy(config.soundCardName,"HPSDR");
strcpy(config.server_address,"127.0.0.1"); // localhost
strcpy(config.share_config_file, getenv("HOME"));
strcat(config.share_config_file, "/dspserver.conf");
processCommands(argc,argv,&config);
#ifdef THREAD_DEBUG
sdr_threads_init();
#endif /* THREAD_DEBUG */
fprintf(stderr, "Reading conf file %s\n", config.share_config_file);
init_register(config.share_config_file); // we now read our conf always
// start web registration if set
if (toShareOrNotToShare) {
fprintf(stderr, "Activating Web register\n");
}
fprintf(stderr,"gHPSDR rx %d (Version %s)\n",receiver,VERSION);
printversion();
setSoundcard(getSoundcardId(config.soundCardName));
// initialize DttSP
if(getcwd(directory, sizeof(directory))==NULL) {
fprintf(stderr,"current working directory path is > MAXPATHLEN");
exit(1);
}
Setup_SDR(directory);
Release_Update();
SetTRX(0,0); // thread 0 is for receive
SetTRX(1,1); // thread 1 is for transmit
SetRingBufferOffset(0,config.offset);
SetThreadProcessingMode(0,RUN_PLAY);
SetThreadProcessingMode(1,RUN_PLAY);
SetSubRXSt(0,1,1);
SetRXOutputGain(0,0,0.20);
SetRXOsc(0,0, -LO_offset);
SetRXOsc(0,1, -LO_offset);
reset_for_buflen(0,1024);
reset_for_buflen(1,1024);
client_init(receiver); // create the main thread responsible for listen TCP socket
// on the read callback:
// accept and interpret the commands from remote GUI
// parse mic data from remote and enque them into Mic_audio_stream queue
// see client.c
//
// on the write callback:
// read the audio_stream_queue and send into the TCP socket
//
audio_stream_init(receiver);
audio_stream_reset();
codec2 = codec2_create(CODEC2_MODE_3200);
G711A_init();
ozy_init(config.server_address); // create and starts iq_thread in ozy.c in order to
// receive iq stream from hardware server
// process it in DttSP
// makes the sample rate adaption for resulting audio
// puts audio stream in a queue (via calls to audio_stream_queue_add
// in audio_stream_put_samples() in audiostream.c)
//
// in case of HPSDR hardware (that is provided with a local D/A converter
// sends via ozy_send() the audio back to the hardware server
SetMode(1, 0, USB);
SetTXFilter(1, 150, 2850);
SetTXOsc(1, LO_offset);
SetTXAMCarrierLevel(1, 0.5);
tx_init(); // create and starts the tx_thread (see client.c)
// the tx_thread reads the Mic_audio_stream queue, makes the sample rate adaption
// process the data into DttSP in order to get the modulation process done,
// and sends back to the hardware server process (via ozy_send() )
#ifdef THREAD_DEBUG
/* Note that some thread interactions will be lost at startup due to
* the fact that the subsystem threads are all started. We can't
* init this until late, though, or we'll catch initializations
* performed at boot time as errors. */
if (config.thread_debug) {
sdr_threads_debug(TRUE);
}
#endif /* THREAD_DEBUG */
while(1) {
sleep(10000);
}
// codec2_destroy(codec2);
return 0;
}
int
main(void)
{
// wdt_disable();
clock_prescale_set(clock_div_1);
MARK433_PORT |= _BV( MARK433_BIT ); // Pull 433MHz marker
MARK915_PORT |= _BV( MARK915_BIT ); // Pull 915MHz marker
led_init();
spi_init();
// Setup the timers. Are needed for watchdog-reset
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
//eeprom_factory_reset("xx");
eeprom_init();
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
//uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
display_channel = DISPLAY_USB;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel |= DISPLAY_RFROUTER;
#endif
checkFrequency();
sei();
for(;;) {
uart_task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_RWE
rf_rwe_task();
#endif
#ifdef HAS_RFNATIVE
native_task();
#endif
#ifdef HAS_KOPP_FC
kopp_fc_task();
#endif
#ifdef HAS_MBUS
rf_mbus_task();
#endif
#ifdef HAS_ZWAVE
rf_zwave_task();
#endif
}
}
int
main(void)
{
wdt_enable(WDTO_2S);
#if defined(CUL_ARDUINO)
clock_prescale_set(clock_div_1); // for 8MHz clock div schould be 1
#endif
MARK433_PORT |= _BV( MARK433_BIT ); // Pull 433MHz marker
MARK915_PORT |= _BV( MARK915_BIT ); // Pull 915MHz marker
// if we had been restarted by watchdog check the REQ BootLoader byte in the
// EEPROM ...
if(bit_is_set(MCUSR,WDRF) && erb(EE_REQBL)) {
ewb( EE_REQBL, 0 ); // clear flag
start_bootloader();
}
// Setup the timers. Are needed for watchdog-reset
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
MCUSR &= ~(1 << WDRF); // Enable the watchdog
led_init();
spi_init();
eeprom_init();
USB_Init();
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel = (DISPLAY_USB|DISPLAY_RFROUTER);
#else
display_channel = DISPLAY_USB;
#endif
checkFrequency();
LED_OFF();
for(;;) {
USB_USBTask();
CDC_Task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_RWE
rf_rwe_task();
#endif
#ifdef HAS_RFNATIVE
native_task();
#endif
#ifdef HAS_KOPP_FC
kopp_fc_task();
#endif
#ifdef HAS_MBUS
rf_mbus_task();
#endif
#ifdef HAS_ZWAVE
rf_zwave_task();
#endif
}
}
int
main(void)
{
wdt_enable(WDTO_2S);
clock_prescale_set(clock_div_1); // Disable Clock Division
// if we had been restarted by watchdog check the REQ BootLoader byte in the
// EEPROM ...
if (bit_is_set(MCUSR,WDRF) && erb(EE_REQBL)) {
ewb( EE_REQBL, 0 ); // clear flag
start_bootloader();
}
// Setup the timers. Are needed for watchdog-reset
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
#ifdef CURV3
// Timer3 is used by the LCD backlight (PWM)
TCCR3A = _BV(COM3A1)| _BV(WGM30); // Fast PWM, 8-bit, clear on match
TCCR3B = _BV(WGM32) | _BV(CS31); // Prescaler 8MHz/8: 3.9KHz
#endif
MCUSR &= ~(1 << WDRF); // Enable the watchdog
led_init();
spi_init();
eeprom_init();
USB_Init();
fht_init();
tx_init();
joy_init(); // lcd init is done manually from menu_init
bat_init();
df_init(&df);
fs_init(&fs, df, 0); // needs df_init
rtc_init(); // does i2c_init too
log_init(); // needs fs_init & rtc_init
menu_init(); // needs fs_init
input_handle_func = analyze_ttydata;
log_enabled = erb(EE_LOGENABLED);
display_channel = DISPLAY_USB|DISPLAY_LCD|DISPLAY_RFROUTER;
rf_router_init();
checkFrequency();
LED_OFF();
for(;;) {
USB_USBTask();
CDC_Task();
RfAnalyze_Task();
Minute_Task();
FastRF_Task();
rf_router_task();
JOY_Task();
}
}
int
main(void)
{
//ewb((uint8_t*)0x80, erb((uint8_t*)0x80)+1);
wdt_enable(WDTO_2S); // Avoid an early reboot
clock_prescale_set(clock_div_1); // Disable Clock Division:1->8MHz
#ifdef HAS_XRAM
init_memory_mapped(); // First initialize the RAM
#endif
// if we had been restarted by watchdog check the REQ BootLoader byte in the
// EEPROM
if(bit_is_set(MCUSR,WDRF) && erb(EE_REQBL)) {
ewb( EE_REQBL, 0 ); // clear flag
start_bootloader();
}
while(tx_report); // reboot if the bss is not initialized
// Setup the timers. Are needed for watchdog-reset
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
MCUSR &= ~(1 << WDRF); // Enable the watchdog
led_init(); // So we can debug
spi_init();
eeprom_init();
USB_Init();
fht_init();
tx_init();
ethernet_init();
#ifdef HAS_FS
df_init(&df);
fs_init(&fs, df, 0); // needs df_init
log_init(); // needs fs_init & rtc_init
log_enabled = erb(EE_LOGENABLED);
#endif
input_handle_func = analyze_ttydata;
display_channel = DISPLAY_USB;
LED_OFF();
for(;;) {
USB_USBTask();
CDC_Task();
RfAnalyze_Task();
Minute_Task();
FastRF_Task();
rf_router_task();
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_ETHERNET
Ethernet_Task();
#endif
}
}
void parse_raw_txack(uint8_t *msg, uint32_t msg_size){
static int32_t state_pos = 0;
static uint8_t *ptr;
static uint8_t var_int_buffer[VAR_INT_BUFFER];
static uint8_t var_int_buffer_index;
static uint32_t seen, script_len;
static uint64_t current_output_val;
for(uint32_t i = 0; i < msg_size; ++i) {
state_pos--;
switch(raw_tx_status) {
case NOT_PARSING:
tx_init(&tp, 0, 0, 0, 0, false);
state_pos = sizeof(uint32_t);
raw_tx_status = PARSING_VERSION;
ptr = (uint8_t *)&tp.version;
case PARSING_VERSION:
*ptr++ = msg[i];
if(state_pos == 1)
{
raw_tx_status = PARSING_INPUT_COUNT;
reset_parsing_buffer(var_int_buffer, &var_int_buffer_index);
}
break;
case PARSING_INPUT_COUNT:
var_int_buffer[var_int_buffer_index++] = msg[i];
if(var_int_buffer_index >= deser_length(var_int_buffer, &tp.inputs_len))
{
raw_tx_status = PARSING_INPUTS;
state_pos = 36;
seen = 0;
reset_parsing_buffer(var_int_buffer, &var_int_buffer_index);
}
break;
case PARSING_INPUTS:
if(state_pos < 0 && seen < tp.inputs_len)
{
var_int_buffer[var_int_buffer_index++] = msg[i];
if(var_int_buffer_index >= deser_length(var_int_buffer, &script_len))
{
seen++;
if(seen < tp.inputs_len)
{
state_pos = script_len + 4 + 36;
}
else
{
state_pos = script_len + 3;
}
script_len = 0;
reset_parsing_buffer(var_int_buffer, &var_int_buffer_index);
}
}
else if(state_pos < 0)
{
raw_tx_status = PARSING_OUTPUT_COUNT;
}
break;
case PARSING_OUTPUT_COUNT:
var_int_buffer[var_int_buffer_index++] = msg[i];
if(var_int_buffer_index >= deser_length(var_int_buffer, &tp.outputs_len))
{
raw_tx_status = PARSING_OUTPUTS_VALUE;
state_pos = 8;
seen = 0;
current_output_val = 0;
ptr = (uint8_t *)¤t_output_val;
reset_parsing_buffer(var_int_buffer, &var_int_buffer_index);
}
break;
case PARSING_OUTPUTS_VALUE:
if(state_pos < 8)
{
*ptr++ = msg[i];
if(state_pos < 1)
{
if (seen == input.prev_index) {
to_spend += current_output_val;
}
raw_tx_status = PARSING_OUTPUTS;
script_len = 0;
reset_parsing_buffer(var_int_buffer, &var_int_buffer_index);
}
}
break;
case PARSING_OUTPUTS:
if(state_pos < 0 && seen < tp.outputs_len)
{
var_int_buffer[var_int_buffer_index++] = msg[i];
if(var_int_buffer_index >= deser_length(var_int_buffer, &script_len))
{
seen++;
if(seen < tp.outputs_len)
{
current_output_val = 0;
ptr = (uint8_t *)¤t_output_val;
raw_tx_status = PARSING_OUTPUTS_VALUE;
state_pos = script_len + 8;
}
else
{
state_pos = script_len - 1;
}
}
}
else if(state_pos < 0)
{
raw_tx_status = PARSING_LOCKTIME;
state_pos = 4;
ptr = (uint8_t *)&tp.lock_time;
reset_parsing_buffer(var_int_buffer, &var_int_buffer_index);
}
break;
case PARSING_LOCKTIME:
if(state_pos >= 0)
{
*ptr++ = msg[i];
}
if(state_pos < 1)
{
raw_tx_status = NOT_PARSING;
memset(&resp, 0, sizeof(TxRequest));
sha256_Update(&(tp.ctx), (const uint8_t*)msg+i, 1);
tx_hash_final(&tp, hash, true);
if (memcmp(hash, input.prev_hash.bytes, 32) != 0) {
fsm_sendFailure(FailureType_Failure_Other, "Encountered invalid prevhash");
signing_abort();
return;
}
if (idx1 < inputs_count - 1) {
idx1++;
send_req_1_input();
} else {
idx1 = 0;
send_req_3_output();
}
return;
}
break;
}
sha256_Update(&(tp.ctx), (const uint8_t*)msg+i, 1);
}
}
void signing_txack(TransactionType *tx)
{
if (!signing) {
fsm_sendFailure(FailureType_Failure_UnexpectedMessage, "Not in Signing mode");
go_home();
return;
}
int co;
memset(&resp, 0, sizeof(TxRequest));
switch (signing_stage) {
case STAGE_REQUEST_1_INPUT:
/* compute multisig fingerprint */
/* (if all input share the same fingerprint, outputs having the same fingerprint will be considered as change outputs) */
if (tx->inputs[0].script_type == InputScriptType_SPENDMULTISIG) {
if (tx->inputs[0].has_multisig && !multisig_fp_mismatch) {
if (multisig_fp_set) {
uint8_t h[32];
if (cryptoMultisigFingerprint(&(tx->inputs[0].multisig), h) == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Error computing multisig fingeprint");
signing_abort();
return;
}
if (memcmp(multisig_fp, h, 32) != 0) {
multisig_fp_mismatch = true;
}
} else {
if (cryptoMultisigFingerprint(&(tx->inputs[0].multisig), multisig_fp) == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Error computing multisig fingeprint");
signing_abort();
return;
}
multisig_fp_set = true;
}
}
} else { // InputScriptType_SPENDADDRESS
multisig_fp_mismatch = true;
}
sha256_Update(&tc, (const uint8_t *)tx->inputs, sizeof(TxInputType));
memcpy(&input, tx->inputs, sizeof(TxInputType));
send_req_2_prev_meta();
return;
case STAGE_REQUEST_2_PREV_META:
tx_init(&tp, tx->inputs_cnt, tx->outputs_cnt, tx->version, tx->lock_time, false);
idx2 = 0;
send_req_2_prev_input();
return;
case STAGE_REQUEST_2_PREV_INPUT:
if (!tx_serialize_input_hash(&tp, tx->inputs)) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to serialize input");
signing_abort();
return;
}
if (idx2 < tp.inputs_len - 1) {
idx2++;
send_req_2_prev_input();
} else {
idx2 = 0;
send_req_2_prev_output();
}
return;
case STAGE_REQUEST_2_PREV_OUTPUT:
if (!tx_serialize_output_hash(&tp, tx->bin_outputs)) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to serialize output");
signing_abort();
return;
}
if (idx2 == input.prev_index) {
to_spend += tx->bin_outputs[0].amount;
}
if (idx2 < tp.outputs_len - 1) {
/* Check prevtx of next input */
idx2++;
send_req_2_prev_output();
} else {
/* Check next output */
tx_hash_final(&tp, hash, true);
if (memcmp(hash, input.prev_hash.bytes, 32) != 0) {
fsm_sendFailure(FailureType_Failure_Other, "Encountered invalid prevhash");
signing_abort();
return;
}
if (idx1 < inputs_count - 1) {
idx1++;
send_req_1_input();
} else {
idx1 = 0;
send_req_3_output();
}
}
return;
case STAGE_REQUEST_3_OUTPUT:
{
/* Downloaded output idx1 the first time.
* Add it to transaction check
* Ask for permission.
*/
bool is_change = false;
if (tx->outputs[0].script_type == OutputScriptType_PAYTOMULTISIG &&
tx->outputs[0].has_multisig &&
multisig_fp_set && !multisig_fp_mismatch) {
uint8_t h[32];
if (cryptoMultisigFingerprint(&(tx->outputs[0].multisig), h) == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Error computing multisig fingeprint");
signing_abort();
return;
}
if (memcmp(multisig_fp, h, 32) == 0) {
is_change = true;
}
} else {
if(tx->outputs[0].has_address_type) {
if(check_valid_output_address(tx->outputs) == false) {
fsm_sendFailure(FailureType_Failure_Other, "Invalid output address type");
signing_abort();
return;
}
if(tx->outputs[0].script_type == OutputScriptType_PAYTOADDRESS &&
tx->outputs[0].address_n_count > 0 &&
tx->outputs[0].address_type == OutputAddressType_CHANGE) {
is_change = true;
}
}
else if(tx->outputs[0].script_type == OutputScriptType_PAYTOADDRESS &&
tx->outputs[0].address_n_count > 0) {
is_change = true;
}
}
if (is_change) {
if (change_spend == 0) { // not set
change_spend = tx->outputs[0].amount;
} else {
fsm_sendFailure(FailureType_Failure_Other, "Only one change output allowed");
signing_abort();
return;
}
}
spending += tx->outputs[0].amount;
co = compile_output(coin, root, tx->outputs, &bin_output, !is_change);
if (co < 0) {
fsm_sendFailure(FailureType_Failure_Other, "Signing cancelled by user");
signing_abort();
return;
} else if (co == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to compile output");
signing_abort();
return;
}
sha256_Update(&tc, (const uint8_t *)&bin_output, sizeof(TxOutputBinType));
if (idx1 < outputs_count - 1) {
idx1++;
send_req_3_output();
} else {
sha256_Final(hash_check, &tc);
// check fees
if (spending > to_spend) {
fsm_sendFailure(FailureType_Failure_NotEnoughFunds, "Not enough funds");
signing_abort();
return;
}
uint64_t fee = to_spend - spending;
uint32_t tx_est_size = transactionEstimateSizeKb(inputs_count, outputs_count);
char total_amount_str[32];
char fee_str[32];
coin_amnt_to_str(coin, fee, fee_str, sizeof(fee_str));
if(fee > (uint64_t)tx_est_size * coin->maxfee_kb) {
if (!confirm(ButtonRequestType_ButtonRequest_FeeOverThreshold,
"Confirm Fee", "%s", fee_str)) {
fsm_sendFailure(FailureType_Failure_ActionCancelled, "Fee over threshold. Signing cancelled.");
signing_abort();
return;
}
}
// last confirmation
coin_amnt_to_str(coin, to_spend - change_spend, total_amount_str, sizeof(total_amount_str));
if(!confirm_transaction(total_amount_str, fee_str))
{
fsm_sendFailure(FailureType_Failure_ActionCancelled, "Signing cancelled by user");
signing_abort();
return;
}
// Everything was checked, now phase 2 begins and the transaction is signed.
layout_simple_message("Signing Transaction...");
idx1 = 0;
idx2 = 0;
send_req_4_input();
}
return;
}
case STAGE_REQUEST_4_INPUT:
if (idx2 == 0) {
tx_init(&ti, inputs_count, outputs_count, version, lock_time, true);
sha256_Init(&tc);
sha256_Update(&tc, (const uint8_t *)&inputs_count, sizeof(inputs_count));
sha256_Update(&tc, (const uint8_t *)&outputs_count, sizeof(outputs_count));
sha256_Update(&tc, (const uint8_t *)&version, sizeof(version));
sha256_Update(&tc, (const uint8_t *)&lock_time, sizeof(lock_time));
memset(privkey, 0, 32);
memset(pubkey, 0, 33);
}
sha256_Update(&tc, (const uint8_t *)tx->inputs, sizeof(TxInputType));
if (idx2 == idx1) {
memcpy(&input, tx->inputs, sizeof(TxInputType));
memcpy(&node, root, sizeof(HDNode));
if (hdnode_private_ckd_cached(&node, tx->inputs[0].address_n, tx->inputs[0].address_n_count) == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to derive private key");
signing_abort();
return;
}
if (tx->inputs[0].script_type == InputScriptType_SPENDMULTISIG) {
if (!tx->inputs[0].has_multisig) {
fsm_sendFailure(FailureType_Failure_Other, "Multisig info not provided");
signing_abort();
return;
}
tx->inputs[0].script_sig.size = compile_script_multisig(&(tx->inputs[0].multisig), tx->inputs[0].script_sig.bytes);
} else { // SPENDADDRESS
ecdsa_get_pubkeyhash(node.public_key, hash);
tx->inputs[0].script_sig.size = compile_script_sig(coin->address_type, hash, tx->inputs[0].script_sig.bytes);
}
if (tx->inputs[0].script_sig.size == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to compile input");
signing_abort();
return;
}
memcpy(privkey, node.private_key, 32);
memcpy(pubkey, node.public_key, 33);
} else {
tx->inputs[0].script_sig.size = 0;
}
if (!tx_serialize_input_hash(&ti, tx->inputs)) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to serialize input");
signing_abort();
return;
}
if (idx2 < inputs_count - 1) {
idx2++;
send_req_4_input();
} else {
idx2 = 0;
send_req_4_output();
}
return;
case STAGE_REQUEST_4_OUTPUT:
co = compile_output(coin, root, tx->outputs, &bin_output, false);
if (co < 0) {
fsm_sendFailure(FailureType_Failure_Other, "Signing cancelled by user");
signing_abort();
return;
} else if (co == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to compile output");
signing_abort();
return;
}
sha256_Update(&tc, (const uint8_t *)&bin_output, sizeof(TxOutputBinType));
if (!tx_serialize_output_hash(&ti, &bin_output)) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to serialize output");
signing_abort();
return;
}
if (idx2 < outputs_count - 1) {
idx2++;
send_req_4_output();
} else {
sha256_Final(hash, &tc);
if (memcmp(hash, hash_check, 32) != 0) {
fsm_sendFailure(FailureType_Failure_Other, "Transaction has changed during signing");
signing_abort();
return;
}
tx_hash_final(&ti, hash, false);
resp.has_serialized = true;
resp.serialized.has_signature_index = true;
resp.serialized.signature_index = idx1;
resp.serialized.has_signature = true;
resp.serialized.has_serialized_tx = true;
ecdsa_sign_digest(&secp256k1, privkey, hash, sig, 0);
resp.serialized.signature.size = ecdsa_sig_to_der(sig, resp.serialized.signature.bytes);
if (input.script_type == InputScriptType_SPENDMULTISIG) {
if (!input.has_multisig) {
fsm_sendFailure(FailureType_Failure_Other, "Multisig info not provided");
signing_abort();
return;
}
// fill in the signature
int pubkey_idx = cryptoMultisigPubkeyIndex(&(input.multisig), pubkey);
if (pubkey_idx < 0) {
fsm_sendFailure(FailureType_Failure_Other, "Pubkey not found in multisig script");
signing_abort();
return;
}
memcpy(input.multisig.signatures[pubkey_idx].bytes, resp.serialized.signature.bytes, resp.serialized.signature.size);
input.multisig.signatures[pubkey_idx].size = resp.serialized.signature.size;
input.script_sig.size = serialize_script_multisig(&(input.multisig), input.script_sig.bytes);
if (input.script_sig.size == 0) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to serialize multisig script");
signing_abort();
return;
}
} else { // SPENDADDRESS
input.script_sig.size = serialize_script_sig(resp.serialized.signature.bytes, resp.serialized.signature.size, pubkey, 33, input.script_sig.bytes);
}
resp.serialized.serialized_tx.size = tx_serialize_input(&to, &input, resp.serialized.serialized_tx.bytes);
if (idx1 < inputs_count - 1) {
idx1++;
idx2 = 0;
send_req_4_input();
} else {
idx1 = 0;
send_req_5_output();
}
}
return;
case STAGE_REQUEST_5_OUTPUT:
if (compile_output(coin, root, tx->outputs, &bin_output,false) <= 0) {
fsm_sendFailure(FailureType_Failure_Other, "Failed to compile output");
signing_abort();
return;
}
resp.has_serialized = true;
resp.serialized.has_serialized_tx = true;
resp.serialized.serialized_tx.size = tx_serialize_output(&to, &bin_output, resp.serialized.serialized_tx.bytes);
if (idx1 < outputs_count - 1) {
idx1++;
send_req_5_output();
} else {
send_req_finished();
signing_abort();
}
return;
}
fsm_sendFailure(FailureType_Failure_Other, "Signing error");
signing_abort();
}
int
main(void)
{
wdt_disable();
led_init();
LED_ON();
MARK433_PORT |= _BV( MARK433_BIT );
MARK915_PORT |= _BV( MARK915_BIT );
spi_init();
// eeprom_factory_reset("xx");
eeprom_init();
// led_mode = 2;
// if we had been restarted by watchdog check the REQ BootLoader byte in the
// EEPROM ...
// if(bit_is_set(MCUSR,WDRF) && eeprom_read_byte(EE_REQBL)) {
// eeprom_write_byte( EE_REQBL, 0 ); // clear flag
// start_bootloader();
// }
// Setup the timers. Are needed for watchdog-reset
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
#ifdef HAS_STACKING
stacking_initialize();
// make sure i2c is inactive
DDRC &= 0xfc;
PORTC &= 0xfc;
#endif
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
display_channel = DISPLAY_USB;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel |= DISPLAY_RFROUTER;
#endif
LED_OFF();
checkFrequency();
sei();
for(;;) {
uart_task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_STACKING
stacking_task();
#endif
#ifdef HAS_MBUS
rf_mbus_task();
#endif
}
}
int
main(void)
{
wdt_disable();
// un-reset ethernet
ENC28J60_RESET_DDR |= _BV( ENC28J60_RESET_BIT );
ENC28J60_RESET_PORT |= _BV( ENC28J60_RESET_BIT );
MARK433_PORT |= _BV( MARK433_BIT ); // Pull 433MHz marker
MARK915_PORT |= _BV( MARK915_BIT ); // Pull 915MHz marker
led_init();
LED_ON();
spi_init();
eeprom_init();
// Reset the "Request Bootloader" flag in EEPROM, to avoid a permanent loop
eeprom_update_byte( EE_REQBL, 0);
// Setup OneWire and make a full search at the beginning (takes some time)
#ifdef HAS_ONEWIRE
i2c_init();
onewire_Init();
onewire_FullSearch();
#endif
// Setup the timers. Are needed for watchdog-reset
#if defined (HAS_IRRX) || defined (HAS_IRTX)
ir_init();
// IR uses highspeed TIMER0 for sampling
OCR0A = 1; // Timer0: 0.008s = 8MHz/256/2 == 15625Hz Fac: 125
#else
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
#endif
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
clock_prescale_set(clock_div_1);
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel = (DISPLAY_USB|DISPLAY_RFROUTER);
#else
display_channel = DISPLAY_USB;
#endif
#ifdef HAS_VZ
vz_init();
#endif
ethernet_init();
LED_OFF();
#ifdef HAS_DMX
#ifdef DMX_CHANNELS
dmx_initialize(DMX_CHANNELS);
#else
dmx_initialize(16);
#endif
#endif
#ifdef HAS_HM485
hm485_initialize();
#endif
#ifdef HAS_HELIOS
helios_initialize();
#endif
#ifdef HAS_CUNOTTY
rf_cunotty_init();
#endif
sei();
#ifdef HAS_DMX
dmx_start();
#endif
for(;;) {
uart_task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_CUNOTTY
rf_cunotty_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_IRRX
ir_task();
#endif
#ifdef HAS_ETHERNET
Ethernet_Task();
#endif
#ifdef HAS_VZ
vz_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_HM485
hm485_task();
#endif
#ifdef HAS_HELIOS
helios_task();
#endif
}
}
int
main(void)
{
wdt_disable();
#ifdef HAS_16MHZ_CLOCK
/* set clock to 16MHz/2 = 8Mhz */
clock_prescale_set(clock_div_2);
#endif
// LED_ON_DDR |= _BV( LED_ON_PIN );
// LED_ON_PORT |= _BV( LED_ON_PIN );
led_init();
LED_ON();
spi_init();
// init_adcw();
//eeprom_factory_reset("xx");
eeprom_init();
// Setup the timers. Are needed for watchdog-reset
OCR0A = 249; // Timer0: 0.008s = 8MHz/256/250 == 125Hz
TCCR0B = _BV(CS02);
TCCR0A = _BV(WGM01);
TIMSK0 = _BV(OCIE0A);
TCCR1A = 0;
TCCR1B = _BV(CS11) | _BV(WGM12); // Timer1: 1us = 8MHz/8
MCUSR &= ~(1 << WDRF); // Enable the watchdog
wdt_enable(WDTO_2S);
#ifdef HAS_16MHZ_CLOCK
uart_init( UART_BAUD_SELECT(UART_BAUD_RATE,F_CPU) );
#else
uart_init( UART_BAUD_SELECT_DOUBLE_SPEED(UART_BAUD_RATE,F_CPU) );
#endif
fht_init();
tx_init();
input_handle_func = analyze_ttydata;
display_channel = DISPLAY_USB;
#ifdef HAS_RF_ROUTER
rf_router_init();
display_channel |= DISPLAY_RFROUTER;
#endif
LED_OFF();
sei();
for(;;) {
uart_task();
RfAnalyze_Task();
Minute_Task();
#ifdef HAS_FASTRF
FastRF_Task();
#endif
#ifdef HAS_RF_ROUTER
rf_router_task();
#endif
#ifdef HAS_ASKSIN
rf_asksin_task();
#endif
#ifdef HAS_MORITZ
rf_moritz_task();
#endif
#ifdef HAS_RWE
rf_rwe_task();
#endif
#ifdef HAS_MBUS
rf_mbus_task();
#endif
}
}
int tx_recv(shpeer_t *cli_peer, tx_t *tx)
{
tx_ledger_t *l;
tx_t *rec_tx;
txop_t *op;
int err;
if (!tx)
return (SHERR_INVAL);
#if 0
if (ledger_tx_load(shpeer_kpriv(cli_peer), tx->hash, tx->tx_stamp)) {
fprintf(stderr, "DEBUG: tx_recv: skipping duplicate tx '%s'\n", tx->hash);
return (SHERR_NOTUNIQ);
}
#endif
op = get_tx_op(tx->tx_op);
if (!op)
return (SHERR_INVAL);
if (tx->tx_flag & TXF_WARD) {
err = txward_confirm(tx);
if (err)
return (err);
}
/* check for dup in ledger (?) */
rec_tx = (tx_t *)tx_load(tx->tx_op, get_tx_key(tx));
if (!rec_tx) {
rec_tx = (tx_t *)calloc(1, op->op_size);
if (!rec_tx)
return (SHERR_NOMEM);
memcpy(rec_tx, tx, op->op_size);
#if 0
err = tx_init(cli_peer, rec_tx);
if (err) {
pstore_free(rec_tx);
return (err);
}
#endif
err = tx_save(rec_tx);
if (err) {
pstore_free(rec_tx);
return (err);
}
}
if (op->op_recv) {
err = op->op_recv(cli_peer, tx);
if (err) {
pstore_free(rec_tx);
return (err);
}
}
pstore_free(rec_tx);
if (is_tx_stored(tx->tx_op)) {
l = ledger_load(shpeer_kpriv(cli_peer), shtime());
if (l) {
ledger_tx_add(l, tx);
ledger_close(l);
}
}
return (0);
}
