void uart_tx_byte(int idx, unsigned char data) { void *base = uart_platform_baseptr(idx); if (!base) return; uart8250_mem_tx_byte(base, data); }
void uart_tx_flush(int idx) { void *base = uart_platform_baseptr(idx); if (!base) return; uart8250_mem_tx_flush(base); }
void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); sifive_uart_init(uart_platform_baseptr(idx), div); }
void uart_init(int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); }
unsigned char uart_rx_byte(int idx) { void *base = uart_platform_baseptr(idx); if (!base) return 0xff; return uart8250_mem_rx_byte(base); }
void uart_tx_byte(int idx, unsigned char data) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); while (!uart_can_tx(regs)) ; /* TODO: implement a timeout */ write32(®s->txdata, data); }
void uart_init(int idx) { struct a10_uart *uart_base = uart_platform_baseptr(idx); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, get_uart_baudrate(), 8, UART_PARITY_NONE, 1); a10_uart_enable_fifos(uart_base); }
void uart_init(int idx) { void *base = uart_platform_baseptr(idx); if (!base) return; unsigned int div; div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16); uart8250_mem_init(base, div); }
void uart_tx_flush(int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t ip; /* Use the TX watermark bit to find out if the TX FIFO is empty */ do { ip = read32(®s->ip); } while (!(ip & IP_TXWM)); }
unsigned char uart_rx_byte(int idx) { struct sifive_uart_registers *regs = uart_platform_baseptr(idx); uint32_t rxdata; do { rxdata = read32(®s->rxdata); } while (rxdata & RXDATA_EMPTY); return rxdata & 0xff; }
void uart_init(int idx) { void *base = uart_platform_baseptr(idx); if (!base) return; unsigned int div; div = uart_baudrate_divisor(get_uart_baudrate(), uart_platform_refclk(), uart_input_clock_divider()); uart8250_mem_init(base, div); }
unsigned char uart_rx_byte(int idx) { return a10_uart_rx_blocking(uart_platform_baseptr(idx)); }
void uart_init(int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_init_dev(uart); }
void uart_tx_byte(int idx, unsigned char data) { struct am335x_uart *uart = uart_platform_baseptr(idx); am335x_uart_tx_byte(uart, data); }
unsigned char uart_rx_byte(int idx) { struct am335x_uart *uart = uart_platform_baseptr(idx); return am335x_uart_rx_byte(uart); }
void uart_tx_byte(int idx, unsigned char data) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_byte(uart, data); }
unsigned char uart_rx_byte(int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); return exynos5_uart_rx_byte(uart); }
void uart_tx_byte(int idx, unsigned char data) { a10_uart_tx_blocking(uart_platform_baseptr(idx), data); }
void uart_tx_flush(int idx) { struct s5p_uart *uart = uart_platform_baseptr(idx); exynos5_uart_tx_flush(uart); }