static int sirfsoc_uart_resume(struct platform_device *pdev)
{
struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
struct uart_port *port = &sirfport->port;
uart_resume_port(&sirfsoc_uart_drv, port);
return 0;
}
static int sw_uart_resume(struct device *dev)
{
#ifdef CONFIG_EVB_PLATFORM
unsigned long flags = 0;
#endif
struct uart_port *port = dev_get_drvdata(dev);
struct sw_uart_port *sw_uport = UART_TO_SPORT(port);
if (port) {
if (SW_UART_NEED_SUSPEND(port)) {
sw_uart_regulator_enable(dev->platform_data);
sw_uart_select_gpio_state(sw_uport->pctrl, PINCTRL_STATE_DEFAULT, sw_uport->id);
}
#ifdef CONFIG_EVB_PLATFORM
/* It's used only in super-standby mode.
FPGA maybe fall into sw_uart_force_lcr(), so comment it. */
if (sw_is_console_port(port) && !console_suspend_enabled) {
spin_lock_irqsave(&port->lock, flags);
sw_uart_reset(sw_uport);
serial_out(port, sw_uport->fcr, SW_UART_FCR);
serial_out(port, sw_uport->mcr, SW_UART_MCR);
serial_out(port, sw_uport->lcr|SW_UART_LCR_DLAB, SW_UART_LCR);
serial_out(port, sw_uport->dll, SW_UART_DLL);
serial_out(port, sw_uport->dlh, SW_UART_DLH);
serial_out(port, sw_uport->lcr, SW_UART_LCR);
serial_out(port, sw_uport->ier, SW_UART_IER);
spin_unlock_irqrestore(&port->lock, flags);
}
#endif
uart_resume_port(&sw_uart_driver, port);
SERIAL_MSG("uart%d resume. DLH: %d, DLL: %d. \n", port->line, sw_uport->dlh, sw_uport->dll);
}
return 0;
}
static int tegra_uart_resume(struct device *dev)
{
struct tegra_uart_port *tup = dev_get_drvdata(dev);
struct uart_port *u = &tup->uport;
return uart_resume_port(&tegra_uart_driver, u);
}
static int msm_serial_resume(struct device *dev)
{
struct uart_port *port;
struct platform_device *pdev = to_platform_device(dev);
port = get_port_from_line(pdev->id);
// BEGIN 0010274: [email protected] 2010-10-27
// Fixed a problem that system don't go to sleep mode.
#if defined(CONFIG_MACH_LGE_BRYCE)
struct msm_port *msm_port;
if(uart_det_flag){
msm_port = UART_TO_MSM(port);
clk_enable(msm_port->clk);
}
#endif
// END 0010274: [email protected] 2010-10-27
if (port) {
if (is_console(port))
msm_init_clock(port);
uart_resume_port(&msm_uart_driver, port);
}
return 0;
}
static int msm_serial_resume(struct platform_device *pdev)
{
struct uart_port *port;
#if defined(CONFIG_KERNEL_MOTOROLA)
struct vreg *vreg;
#endif /* defined(CONFIG_KERNEL_MOTOROLA) */
port = get_port_from_line(pdev->id);
if (port) {
#if defined(CONFIG_KERNEL_MOTOROLA)
/* Calgary uses VREG_USIM (RUIM1) for the UART3 block */
if (pdev->id == 2)
{
vreg = vreg_get(0, "ruim");
if (IS_ERR(vreg))
printk(KERN_ERR "%s: vreg get failed for VREG_RUIM\n", __func__);
else if (vreg_enable(vreg))
printk(KERN_ERR "%s: vreg enable failed for VREG_RUIM\n", __func__);
else
printk(KERN_INFO "%s: VREG_RUIM enabled for RS232\n", __func__);
}
#endif /* defined(CONFIG_KERNEL_MOTOROLA) */
if (is_console(port))
msm_init_clock(port);
uart_resume_port(&msm_uart_driver, port);
}
return 0;
}
static int msm_serial_hsl_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct msm_hsl_port *msm_cir_port = htc_cir_port;
struct uart_port *port;
port = get_port_from_line(pdev->id);
D("%s ():port->line %d, cir_enable_flg = %d\n",
__func__, port->line, cir_enable_flg);
if (msm_cir_port->cir_power)
msm_cir_port->cir_power(1);
if (port) {
if (msm_cir_port->cir_set_path)
msm_cir_port->cir_set_path(cir_enable_flg);
uart_resume_port(&msm_hsl_uart_driver, port);
if (device_may_wakeup(dev))
disable_irq_wake(port->irq);
if (is_console(port))
msm_hsl_init_clock(port);
}
return 0;
}
static int serial_omap_resume(struct device *dev)
{
struct uart_omap_port *up = dev_get_drvdata(dev);
if (up)
uart_resume_port(&serial_omap_reg, &up->port);
return 0;
}
static int sprd_resume(struct device *dev)
{
struct sprd_uart_port *sup = dev_get_drvdata(dev);
uart_resume_port(&sprd_uart_driver, &sup->port);
return 0;
}
static int serial_m3110_resume(struct spi_device *spi)
{
struct uart_max3110 *max = spi_get_drvdata(spi);
max3110_out(max, max->cur_conf);
uart_resume_port(&serial_m3110_reg, &max->port);
enable_irq(max->irq);
return 0;
}
static int pl010_resume(struct amba_device *dev)
{
struct uart_amba_port *uap = amba_get_drvdata(dev);
if (uap)
uart_resume_port(&amba_reg, &uap->port);
return 0;
}
static int serial_netx_resume(struct platform_device *pdev)
{
struct netx_port *sport = platform_get_drvdata(pdev);
if (sport)
uart_resume_port(&netx_reg, &sport->port);
return 0;
}
static int stm32_serial_resume(struct device *dev)
{
struct uart_port *port = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
stm32_serial_enable_wakeup(port, false);
return uart_resume_port(&stm32_usart_driver, port);
}
static int ip3106_serial_resume(struct device *_dev, u32 level)
{
struct ip3106_port *sport = dev_get_drvdata(_dev);
if (sport && level == RESUME_ENABLE)
uart_resume_port(&ip3106_reg, &sport->port);
return 0;
}
static int sa1100_serial_resume(struct platform_device *dev)
{
struct sa1100_port *sport = platform_get_drvdata(dev);
if (sport)
uart_resume_port(&sa1100_reg, &sport->port);
return 0;
}
static int serial_pxa_resume(struct device *dev)
{
struct uart_pxa_port *sport = dev_get_drvdata(dev);
if (sport)
uart_resume_port(&serial_pxa_reg, &sport->port);
return 0;
}
static int parrot5_serial_resume(struct platform_device *dev)
{
struct uart_parrot5_port *up = platform_get_drvdata(dev);
if (up) {
uart_resume_port(&parrot5_reg, &up->port);
}
return 0;
}
static int serial_omap_resume(struct device *dev)
{
struct uart_omap_port *up = dev_get_drvdata(dev);
if (up) {
uart_resume_port(&serial_omap_reg, &up->port);
up->suspended = false;
}
return 0;
}
/**
* xuartps_resume - Resume after a previous suspend
* @device: Pointer to the device structure
*
* Returns 0
*/
static int xuartps_resume(struct device *device)
{
struct uart_port *port = dev_get_drvdata(device);
unsigned long flags = 0;
u32 ctrl_reg;
struct tty_struct *tty;
struct device *tty_dev;
int may_wake = 0;
/* Get the tty which could be NULL so don't assume it's valid */
tty = tty_port_tty_get(&port->state->port);
if (tty) {
tty_dev = tty->dev;
may_wake = device_may_wakeup(tty_dev);
tty_kref_put(tty);
}
if (console_suspend_enabled && !may_wake) {
struct xuartps *xuartps = port->private_data;
clk_enable(xuartps->aperclk);
clk_enable(xuartps->refclk);
spin_lock_irqsave(&port->lock, flags);
/* Set TX/RX Reset */
xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
XUARTPS_CR_OFFSET);
while (xuartps_readl(XUARTPS_CR_OFFSET) &
(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST))
cpu_relax();
/* restore rx timeout value */
xuartps_writel(rx_timeout, XUARTPS_RXTOUT_OFFSET);
/* Enable Tx/Rx */
ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
xuartps_writel(
(ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS)) |
(XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
XUARTPS_CR_OFFSET);
spin_unlock_irqrestore(&port->lock, flags);
} else {
spin_lock_irqsave(&port->lock, flags);
/* restore original rx trigger level */
xuartps_writel(rx_trigger_level, XUARTPS_RXWM_OFFSET);
/* enable RX timeout interrupt */
xuartps_writel(XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
spin_unlock_irqrestore(&port->lock, flags);
}
return uart_resume_port(&xuartps_uart_driver, port);
}
static int serial_omap_resume(struct device *dev)
{
struct uart_omap_port *up = dev_get_drvdata(dev);
if (device_may_wakeup(dev))
serial_omap_enable_wakeup(up, false);
uart_resume_port(&serial_omap_reg, &up->port);
return 0;
}
static int serial_m3110_resume(struct device *dev)
{
struct spi_device *spi = to_spi_device(dev);
struct uart_max3110 *max = spi_get_drvdata(spi);
/* Enable IRQ before max3110 write */
if (max->irq > 0)
enable_irq(max->irq);
max3110_out(max, max->cur_conf);
uart_resume_port(&serial_m3110_reg, &max->port);
return 0;
}
static int __maybe_unused max310x_resume(struct device *dev)
{
struct max310x_port *s = dev_get_drvdata(dev);
int i;
for (i = 0; i < s->uart.nr; i++) {
s->devtype->power(&s->p[i].port, 1);
uart_resume_port(&s->uart, &s->p[i].port);
}
return 0;
}
static int bfin_serial_resume(struct platform_device *dev)
{
int i;
for (i = 0; i < nr_active_ports; i++) {
if (bfin_serial_ports[i].port.dev != &dev->dev)
continue;
uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
}
return 0;
}
/**
* cdns_uart_resume - Resume after a previous suspend
* @device: Pointer to the device structure
*
* Return: 0
*/
static int cdns_uart_resume(struct device *device)
{
struct uart_port *port = dev_get_drvdata(device);
unsigned long flags = 0;
u32 ctrl_reg;
struct tty_struct *tty;
struct device *tty_dev;
int may_wake = 0;
/* Get the tty which could be NULL so don't assume it's valid */
tty = tty_port_tty_get(&port->state->port);
if (tty) {
tty_dev = tty->dev;
may_wake = device_may_wakeup(tty_dev);
tty_kref_put(tty);
}
if (console_suspend_enabled && !may_wake) {
struct cdns_uart *cdns_uart = port->private_data;
clk_enable(cdns_uart->pclk);
clk_enable(cdns_uart->uartclk);
spin_lock_irqsave(&port->lock, flags);
/* Set TX/RX Reset */
ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
cpu_relax();
/* restore rx timeout value */
cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
/* Enable Tx/Rx */
ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
spin_unlock_irqrestore(&port->lock, flags);
} else {
spin_lock_irqsave(&port->lock, flags);
/* restore original rx trigger level */
cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
/* enable RX timeout interrupt */
cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET);
spin_unlock_irqrestore(&port->lock, flags);
}
return uart_resume_port(&cdns_uart_uart_driver, port);
}
static int msm_serial_resume(struct platform_device *pdev)
{
struct uart_port *port;
port = get_port_from_line(pdev->id);
if (port) {
if (is_console(port))
msm_init_clock(port);
uart_resume_port(&msm_uart_driver, port);
}
return 0;
}
static int atmel_serial_resume(struct platform_device *pdev)
{
struct uart_port *port = platform_get_drvdata(pdev);
struct atmel_uart_port *atmel_port = (struct atmel_uart_port *) port;
if (atmel_port->suspended) {
uart_resume_port(&atmel_uart, port);
atmel_port->suspended = 0;
}
else
disable_irq_wake(port->irq);
return 0;
}
static int serial_hs_lpc32xx_resume(struct platform_device *dev)
{
int i;
for (i = 0; i < uarts_registered; i++) {
struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[i];
if (p->port.type != PORT_UNKNOWN && p->port.dev == &dev->dev)
uart_resume_port(&lpc32xx_hs_reg, &p->port);
}
return 0;
}
static int serial_omap_resume(struct platform_device *dev)
{
struct uart_omap_port *up = platform_get_drvdata(dev);
struct omap_uart_port_info *omap_up_info = dev->dev.platform_data;
if (omap_is_console_port(&up->port) && up->plat_hold_wakelock &&
omap_up_info->uart_wakeup_event)
up->plat_hold_wakelock(up, WAKELK_RESUME);
if (up)
uart_resume_port(&serial_omap_reg, &up->port);
return 0;
}
static int serial_omap_resume(struct device *dev)
{
struct uart_omap_port *up = dev_get_drvdata(dev);
/* Select default pin state */
pinctrl_pm_select_default_state(dev);
if (device_may_wakeup(dev))
serial_omap_enable_wakeup(up, false);
uart_resume_port(&serial_omap_reg, &up->port);
return 0;
}
static int s3c24xx_serial_resume(struct platform_device *dev)
{
struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
struct s3c24xx_uart_port *ourport = to_ourport(port);
if (port) {
clk_enable(ourport->clk);
s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
clk_disable(ourport->clk);
uart_resume_port(&s3c24xx_uart_drv, port);
}
return 0;
}
static int tegra_uart_resume(struct platform_device *pdev)
{
struct tegra_uart_port *t = platform_get_drvdata(pdev);
struct uart_port *u;
if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
pr_err("Invalid Uart instance (%d)\n", pdev->id);
u = &t->uport;
dev_dbg(t->uport.dev, "tegra_uart_resume called\n");
if (t->uart_state == TEGRA_UART_SUSPEND)
uart_resume_port(&tegra_uart_driver, u);
return 0;
}
