/*
* Initialize a TS device. Set up UBA mapping registers,
* initialize data structures, what else ???
*/
void
tsinit(struct ts_softc *sc)
{
if (sc->sc_mapped == 0) {
/*
* Map the communications area and command and message
* buffer into Unibus address space.
*/
sc->sc_ui.ui_size = sizeof(struct ts);
if (ubmemalloc(sc->sc_uh, &sc->sc_ui, UBA_CANTWAIT))
return;
sc->sc_vts = (void *)sc->sc_ui.ui_vaddr;
sc->sc_bts = (void *)sc->sc_ui.ui_baddr;
sc->sc_waddr = sc->sc_ui.ui_baddr |
((sc->sc_ui.ui_baddr >> 16) & 3);
sc->sc_mapped = 1;
}
/*
* Initialization of interface; clear recorded pending
* operations, and reinitialize UNIBUS usage.
*/
int
deinit(struct ifnet *ifp)
{
struct de_softc *sc = ifp->if_softc;
struct de_cdata *dc, *pdc;
struct ifrw *ifrw;
struct ifxmt *ifxp;
struct de_ring *rp;
int s, error;
if (ifp->if_flags & IFF_RUNNING)
return 0;
if ((sc->sc_flags & DSF_MAPPED) == 0) {
if (if_ubaminit(&sc->sc_ifuba, (void *)sc->sc_dev.dv_parent,
MCLBYTES, sc->sc_ifr, NRCV, sc->sc_ifw, NXMT)) {
printf("%s: can't initialize\n", sc->sc_dev.dv_xname);
ifp->if_flags &= ~IFF_UP;
return 0;
}
sc->sc_ui.ui_size = sizeof(struct de_cdata);
if ((error = ubmemalloc((void *)sc->sc_dev.dv_parent,
&sc->sc_ui, 0))) {
printf(": unable to ubmemalloc(), error = %d\n", error);
return 0;
}
sc->sc_pdedata = (struct de_cdata *)sc->sc_ui.ui_baddr;
sc->sc_dedata = (struct de_cdata *)sc->sc_ui.ui_vaddr;
sc->sc_flags |= DSF_MAPPED;
}
/*
* Tell the DEUNA about our PCB
*/
DE_WCSR(DE_PCSR2, LOWORD(sc->sc_pdedata));
DE_WCSR(DE_PCSR3, HIWORD(sc->sc_pdedata));
DE_WLOW(0); /* reset INTE */
DELAY(500);
DE_WLOW(CMD_GETPCBB);
dewait(sc, "pcbb");
dc = sc->sc_dedata;
pdc = sc->sc_pdedata;
/* set the transmit and receive ring header addresses */
dc->dc_pcbb.pcbb0 = FC_WTRING;
dc->dc_pcbb.pcbb2 = LOWORD(&pdc->dc_udbbuf);
dc->dc_pcbb.pcbb4 = HIWORD(&pdc->dc_udbbuf);
dc->dc_udbbuf.b_tdrbl = LOWORD(&pdc->dc_xrent[0]);
dc->dc_udbbuf.b_tdrbh = HIWORD(&pdc->dc_xrent[0]);
dc->dc_udbbuf.b_telen = sizeof (struct de_ring) / sizeof(u_int16_t);
dc->dc_udbbuf.b_trlen = NXMT;
dc->dc_udbbuf.b_rdrbl = LOWORD(&pdc->dc_rrent[0]);
dc->dc_udbbuf.b_rdrbh = HIWORD(&pdc->dc_rrent[0]);
dc->dc_udbbuf.b_relen = sizeof (struct de_ring) / sizeof(u_int16_t);
dc->dc_udbbuf.b_rrlen = NRCV;
DE_WLOW(CMD_GETCMD);
dewait(sc, "wtring");
sc->sc_dedata->dc_pcbb.pcbb0 = FC_WTMODE;
sc->sc_dedata->dc_pcbb.pcbb2 = MOD_TPAD|MOD_HDX|MOD_DRDC|MOD_ENAL;
DE_WLOW(CMD_GETCMD);
dewait(sc, "wtmode");
/* set up the receive and transmit ring entries */
ifxp = &sc->sc_ifw[0];
for (rp = &dc->dc_xrent[0]; rp < &dc->dc_xrent[NXMT]; rp++) {
rp->r_segbl = LOWORD(ifxp->ifw_info);
rp->r_segbh = HIWORD(ifxp->ifw_info);
rp->r_flags = 0;
ifxp++;
}
ifrw = &sc->sc_ifr[0];
for (rp = &dc->dc_rrent[0]; rp < &dc->dc_rrent[NRCV]; rp++) {
rp->r_slen = MCLBYTES - 2;
rp->r_segbl = LOWORD(ifrw->ifrw_info);
rp->r_segbh = HIWORD(ifrw->ifrw_info);
rp->r_flags = RFLG_OWN;
ifrw++;
}
/* start up the board (rah rah) */
s = splnet();
sc->sc_rindex = sc->sc_xindex = sc->sc_xfree = sc->sc_nxmit = 0;
sc->sc_if.if_flags |= IFF_RUNNING;
DE_WLOW(PCSR0_INTE); /* avoid interlock */
destart(&sc->sc_if); /* queue output packets */
DE_WLOW(CMD_START|PCSR0_INTE);
splx(s);
return 0;
}
/*
* Interface exists: make available by filling in network interface
* record. System will initialize the interface when it is ready
* to accept packets. We get the ethernet address here.
*/
void
deattach(struct device *parent, struct device *self, void *aux)
{
struct uba_attach_args *ua = aux;
struct de_softc *sc = (struct de_softc *)self;
struct ifnet *ifp = &sc->sc_if;
u_int8_t myaddr[ETHER_ADDR_LEN];
int csr1, error;
char *c;
sc->sc_iot = ua->ua_iot;
sc->sc_ioh = ua->ua_ioh;
sc->sc_dmat = ua->ua_dmat;
/*
* What kind of a board is this?
* The error bits 4-6 in pcsr1 are a device id as long as
* the high byte is zero.
*/
csr1 = DE_RCSR(DE_PCSR1);
if (csr1 & 0xff60)
c = "broken";
else if (csr1 & 0x10)
c = "delua";
else
c = "deuna";
/*
* Reset the board and temporarily map
* the pcbb buffer onto the Unibus.
*/
DE_WCSR(DE_PCSR0, 0); /* reset INTE */
DELAY(100);
DE_WCSR(DE_PCSR0, PCSR0_RSET);
dewait(sc, "reset");
sc->sc_ui.ui_size = sizeof(struct de_cdata);
if ((error = ubmemalloc((struct uba_softc *)parent, &sc->sc_ui, 0)))
return printf(": failed ubmemalloc(), error = %d\n", error);
sc->sc_dedata = (struct de_cdata *)sc->sc_ui.ui_vaddr;
/*
* Tell the DEUNA about our PCB
*/
DE_WCSR(DE_PCSR2, LOWORD(sc->sc_ui.ui_baddr));
DE_WCSR(DE_PCSR3, HIWORD(sc->sc_ui.ui_baddr));
DE_WLOW(CMD_GETPCBB);
dewait(sc, "pcbb");
sc->sc_dedata->dc_pcbb.pcbb0 = FC_RDPHYAD;
DE_WLOW(CMD_GETCMD);
dewait(sc, "read addr ");
bcopy((caddr_t)&sc->sc_dedata->dc_pcbb.pcbb2, myaddr, sizeof (myaddr));
printf(": %s, address %s\n", c, ether_sprintf(myaddr));
uba_intr_establish(ua->ua_icookie, ua->ua_cvec, deintr, sc,
&sc->sc_intrcnt);
uba_reset_establish(dereset, &sc->sc_dev);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
sc->sc_dev.dv_xname, "intr");
strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST|IFF_ALLMULTI;
ifp->if_ioctl = deioctl;
ifp->if_start = destart;
ifp->if_init = deinit;
ifp->if_stop = destop;
IFQ_SET_READY(&ifp->if_snd);
if_attach(ifp);
ether_ifattach(ifp, myaddr);
ubmemfree((struct uba_softc *)parent, &sc->sc_ui);
sc->sc_sh = shutdownhook_establish(deshutdown, sc);
}
/*
* Interface exists: make available by filling in network interface
* record. System will initialize the interface when it is ready
* to accept packets.
*/
void
qeattach(device_t parent, device_t self, void *aux)
{
struct uba_attach_args *ua = aux;
struct qe_softc *sc = device_private(self);
struct ifnet *ifp = &sc->sc_if;
struct qe_ring *rp;
u_int8_t enaddr[ETHER_ADDR_LEN];
int i, error;
char *nullbuf;
sc->sc_dev = self;
sc->sc_uh = device_private(parent);
sc->sc_iot = ua->ua_iot;
sc->sc_ioh = ua->ua_ioh;
sc->sc_dmat = ua->ua_dmat;
/*
* Allocate DMA safe memory for descriptors and setup memory.
*/
sc->sc_ui.ui_size = sizeof(struct qe_cdata) + ETHER_PAD_LEN;
if ((error = ubmemalloc(sc->sc_uh, &sc->sc_ui, 0))) {
aprint_error(": unable to ubmemalloc(), error = %d\n", error);
return;
}
sc->sc_pqedata = (struct qe_cdata *)sc->sc_ui.ui_baddr;
sc->sc_qedata = (struct qe_cdata *)sc->sc_ui.ui_vaddr;
/*
* Zero the newly allocated memory.
*/
memset(sc->sc_qedata, 0, sizeof(struct qe_cdata) + ETHER_PAD_LEN);
nullbuf = ((char*)sc->sc_qedata) + sizeof(struct qe_cdata);
/*
* Create the transmit descriptor DMA maps. We take advantage
* of the fact that the Qbus address space is big, and therefore
* allocate map registers for all transmit descriptors also,
* so that we can avoid this each time we send a packet.
*/
for (i = 0; i < TXDESCS; i++) {
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
&sc->sc_xmtmap[i]))) {
aprint_error(
": unable to create tx DMA map %d, error = %d\n",
i, error);
goto fail_4;
}
}
/*
* Create receive buffer DMA maps.
*/
for (i = 0; i < RXDESCS; i++) {
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT,
&sc->sc_rcvmap[i]))) {
aprint_error(
": unable to create rx DMA map %d, error = %d\n",
i, error);
goto fail_5;
}
}
/*
* Pre-allocate the receive buffers.
*/
for (i = 0; i < RXDESCS; i++) {
if ((error = qe_add_rxbuf(sc, i)) != 0) {
aprint_error(
": unable to allocate or map rx buffer %d,"
" error = %d\n", i, error);
goto fail_6;
}
}
if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1,
ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) {
aprint_error(
": unable to create pad buffer DMA map, error = %d\n",
error);
goto fail_6;
}
if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap,
nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) {
aprint_error(
": unable to load pad buffer DMA map, error = %d\n",
error);
goto fail_7;
}
bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN,
BUS_DMASYNC_PREWRITE);
/*
* Create ring loops of the buffer chains.
* This is only done once.
*/
rp = sc->sc_qedata->qc_recv;
rp[RXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_recv[0]);
rp[RXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_recv[0]) |
QE_VALID | QE_CHAIN;
rp[RXDESCS].qe_flag = rp[RXDESCS].qe_status1 = QE_NOTYET;
rp = sc->sc_qedata->qc_xmit;
rp[TXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_xmit[0]);
rp[TXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_xmit[0]) |
QE_VALID | QE_CHAIN;
rp[TXDESCS].qe_flag = rp[TXDESCS].qe_status1 = QE_NOTYET;
/*
* Get the vector that were set at match time, and remember it.
*/
sc->sc_intvec = sc->sc_uh->uh_lastiv;
QE_WCSR(QE_CSR_CSR, QE_RESET);
DELAY(1000);
QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);
/*
* Read out ethernet address and tell which type this card is.
*/
for (i = 0; i < 6; i++)
enaddr[i] = QE_RCSR(i * 2) & 0xff;
QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec | 1);
aprint_normal(": %s, hardware address %s\n",
QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa":"deqna",
ether_sprintf(enaddr));
QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */
uba_intr_establish(ua->ua_icookie, ua->ua_cvec, qeintr,
sc, &sc->sc_intrcnt);
evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, ua->ua_evcnt,
device_xname(sc->sc_dev), "intr");
strcpy(ifp->if_xname, device_xname(sc->sc_dev));
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_start = qestart;
ifp->if_ioctl = qeioctl;
ifp->if_watchdog = qetimeout;
IFQ_SET_READY(&ifp->if_snd);
/*
* Attach the interface.
*/
if_attach(ifp);
ether_ifattach(ifp, enaddr);
return;
/*
* Free any resources we've allocated during the failed attach
* attempt. Do this in reverse order and fall through.
*/
fail_7:
bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap);
fail_6:
for (i = 0; i < RXDESCS; i++) {
if (sc->sc_rxmbuf[i] != NULL) {
bus_dmamap_unload(sc->sc_dmat, sc->sc_rcvmap[i]);
m_freem(sc->sc_rxmbuf[i]);
}
}
fail_5:
for (i = 0; i < RXDESCS; i++) {
if (sc->sc_rcvmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]);
}
fail_4:
for (i = 0; i < TXDESCS; i++) {
if (sc->sc_xmtmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]);
}
}
/*
* Interface exists: make available by filling in network interface
* record. System will initialize the interface when it is ready
* to accept packets.
*/
void
qeattach(struct device *parent, struct device *self, void *aux)
{
struct uba_attach_args *ua = aux;
struct uba_softc *ubasc = (struct uba_softc *)parent;
struct qe_softc *sc = (struct qe_softc *)self;
struct ifnet *ifp = (struct ifnet *)&sc->sc_if;
struct qe_ring *rp;
int i, error;
sc->sc_iot = ua->ua_iot;
sc->sc_ioh = ua->ua_ioh;
sc->sc_dmat = ua->ua_dmat;
/*
* Allocate DMA safe memory for descriptors and setup memory.
*/
sc->sc_ui.ui_size = sizeof(struct qe_cdata);
if ((error = ubmemalloc((struct uba_softc *)parent, &sc->sc_ui, 0))) {
printf(": unable to ubmemalloc(), error = %d\n", error);
return;
}
sc->sc_pqedata = (struct qe_cdata *)sc->sc_ui.ui_baddr;
sc->sc_qedata = (struct qe_cdata *)sc->sc_ui.ui_vaddr;
/*
* Zero the newly allocated memory.
*/
bzero(sc->sc_qedata, sizeof(struct qe_cdata));
/*
* Create the transmit descriptor DMA maps. We take advantage
* of the fact that the Qbus address space is big, and therefore
* allocate map registers for all transmit descriptors also,
* so that we can avoid this each time we send a packet.
*/
for (i = 0; i < TXDESCS; i++) {
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
1, MCLBYTES, 0, BUS_DMA_NOWAIT|BUS_DMA_ALLOCNOW,
&sc->sc_xmtmap[i]))) {
printf(": unable to create tx DMA map %d, error = %d\n",
i, error);
goto fail_4;
}
}
/*
* Create receive buffer DMA maps.
*/
for (i = 0; i < RXDESCS; i++) {
if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
MCLBYTES, 0, BUS_DMA_NOWAIT,
&sc->sc_rcvmap[i]))) {
printf(": unable to create rx DMA map %d, error = %d\n",
i, error);
goto fail_5;
}
}
/*
* Pre-allocate the receive buffers.
*/
for (i = 0; i < RXDESCS; i++) {
if ((error = qe_add_rxbuf(sc, i)) != 0) {
printf(": unable to allocate or map rx buffer %d\n,"
" error = %d\n", i, error);
goto fail_6;
}
}
/*
* Create ring loops of the buffer chains.
* This is only done once.
*/
rp = sc->sc_qedata->qc_recv;
rp[RXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_recv[0]);
rp[RXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_recv[0]) |
QE_VALID | QE_CHAIN;
rp[RXDESCS].qe_flag = rp[RXDESCS].qe_status1 = QE_NOTYET;
rp = sc->sc_qedata->qc_xmit;
rp[TXDESCS].qe_addr_lo = LOWORD(&sc->sc_pqedata->qc_xmit[0]);
rp[TXDESCS].qe_addr_hi = HIWORD(&sc->sc_pqedata->qc_xmit[0]) |
QE_VALID | QE_CHAIN;
rp[TXDESCS].qe_flag = rp[TXDESCS].qe_status1 = QE_NOTYET;
/*
* Get the vector that were set at match time, and remember it.
*/
sc->sc_intvec = ubasc->uh_lastiv;
QE_WCSR(QE_CSR_CSR, QE_RESET);
DELAY(1000);
QE_WCSR(QE_CSR_CSR, QE_RCSR(QE_CSR_CSR) & ~QE_RESET);
/*
* Read out ethernet address and tell which type this card is.
*/
for (i = 0; i < 6; i++)
sc->sc_ac.ac_enaddr[i] = QE_RCSR(i * 2) & 0xff;
QE_WCSR(QE_CSR_VECTOR, sc->sc_intvec | 1);
printf(": %s, address %s\n",
QE_RCSR(QE_CSR_VECTOR) & 1 ? "delqa" : "deqna",
ether_sprintf(sc->sc_ac.ac_enaddr));
QE_WCSR(QE_CSR_VECTOR, QE_RCSR(QE_CSR_VECTOR) & ~1); /* ??? */
uba_intr_establish(ua->ua_icookie, ua->ua_cvec, qeintr,
sc, &sc->sc_intrcnt);
sc->sc_cvec = ua->ua_cvec;
evcount_attach(&sc->sc_intrcnt, sc->sc_dev.dv_xname, &sc->sc_cvec);
strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname);
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_start = qestart;
ifp->if_ioctl = qeioctl;
ifp->if_watchdog = qetimeout;
IFQ_SET_READY(&ifp->if_snd);
/*
* Attach the interface.
*/
if_attach(ifp);
ether_ifattach(ifp);
return;
/*
* Free any resources we've allocated during the failed attach
* attempt. Do this in reverse order and fall through.
*/
fail_6:
for (i = 0; i < RXDESCS; i++) {
if (sc->sc_rxmbuf[i] != NULL) {
bus_dmamap_unload(sc->sc_dmat, sc->sc_xmtmap[i]);
m_freem(sc->sc_rxmbuf[i]);
}
}
fail_5:
for (i = 0; i < RXDESCS; i++) {
if (sc->sc_xmtmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_xmtmap[i]);
}
fail_4:
for (i = 0; i < TXDESCS; i++) {
if (sc->sc_rcvmap[i] != NULL)
bus_dmamap_destroy(sc->sc_dmat, sc->sc_rcvmap[i]);
}
}
