static int simple_panel_ofdata_to_platdata(struct udevice *dev)
{
struct simple_panel_priv *priv = dev_get_priv(dev);
int ret;
if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret) {
debug("%s: Warning: cannot get power supply: ret=%d\n",
__func__, ret);
if (ret != -ENOENT)
return ret;
}
}
ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
"backlight", &priv->backlight);
if (ret) {
debug("%s: Cannot get backlight: ret=%d\n", __func__, ret);
return ret;
}
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
debug("%s: Warning: cannot get enable GPIO: ret=%d\n",
__func__, ret);
if (ret != -ENOENT)
return ret;
}
return 0;
}
int syscon_reboot_probe(struct udevice *dev)
{
struct udevice *syscon;
struct syscon_reboot_priv *priv = dev_get_priv(dev);
int err;
err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
"regmap", &syscon);
if (err) {
error("unable to find syscon device\n");
return err;
}
priv->regmap = syscon_get_regmap(syscon);
if (!priv->regmap) {
error("unable to find regmap\n");
return -ENODEV;
}
priv->offset = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"offset", 0);
priv->mask = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"mask", 0);
return 0;
}
struct regmap *syscon_regmap_lookup_by_phandle(struct udevice *dev,
const char *name)
{
struct udevice *syscon;
struct regmap *r;
u32 phandle;
ofnode node;
int err;
err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
name, &syscon);
if (err) {
/* found node with "syscon" compatible, not bounded to SYSCON */
err = ofnode_read_u32(dev_ofnode(dev), name, &phandle);
if (err)
return ERR_PTR(err);
node = ofnode_get_by_phandle(phandle);
if (!ofnode_valid(node)) {
dev_dbg(dev, "unable to find syscon device\n");
return ERR_PTR(-EINVAL);
}
err = syscon_probe_by_ofnode(node, &syscon);
if (err)
return ERR_PTR(-ENODEV);
}
r = syscon_get_regmap(syscon);
if (!r) {
dev_dbg(dev, "unable to find regmap\n");
return ERR_PTR(-ENODEV);
}
return r;
}
static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
int index, ret, count, len;
const u32 *cell;
log_debug("start\n");
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret)
log_debug("Cannot get power supply: ret=%d\n", ret);
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
log_debug("Warning: cannot get enable GPIO: ret=%d\n", ret);
if (ret != -ENOENT)
return log_ret(ret);
}
ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,
&args);
if (ret) {
log_debug("Cannot get PWM phandle: ret=%d\n", ret);
return log_ret(ret);
}
ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
log_debug("Cannot get PWM: ret=%d\n", ret);
return log_ret(ret);
}
if (args.args_count < 2)
return log_msg_ret("Not enough arguments to pwm\n", -EINVAL);
priv->channel = args.args[0];
priv->period_ns = args.args[1];
if (args.args_count > 2)
priv->polarity = args.args[2];
index = dev_read_u32_default(dev, "default-brightness-level", 255);
cell = dev_read_prop(dev, "brightness-levels", &len);
count = len / sizeof(u32);
if (cell && count > index) {
priv->levels = malloc(len);
if (!priv->levels)
return log_ret(-ENOMEM);
dev_read_u32_array(dev, "brightness-levels", priv->levels,
count);
priv->num_levels = count;
priv->default_level = priv->levels[index];
priv->max_level = priv->levels[count - 1];
} else {
priv->default_level = index;
priv->max_level = 255;
}
priv->cur_level = priv->default_level;
log_debug("done\n");
return 0;
}
static int rockchip_dwmmc_probe(struct udevice *dev)
{
struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
struct udevice *pwr_dev __maybe_unused;
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
host->name = dev->name;
host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
host->buswidth = dtplat->bus_width;
host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
host->priv = dev;
host->dev_index = 0;
priv->fifo_depth = dtplat->fifo_depth;
priv->fifo_mode = 0;
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = dtplat->max_frequency;
ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
if (ret < 0)
return ret;
#else
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret < 0)
return ret;
#endif
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(priv->fifo_depth / 2 - 1) |
TX_WMARK(priv->fifo_depth / 2);
host->fifo_mode = priv->fifo_mode;
#ifdef CONFIG_PWRSEQ
/* Enable power if needed */
ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
&pwr_dev);
if (!ret) {
ret = pwrseq_set_power(pwr_dev, true);
if (ret)
return ret;
}
#endif
dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
host->mmc = &plat->mmc;
host->mmc->priv = &priv->host;
host->mmc->dev = dev;
upriv->mmc = host->mmc;
return dwmci_probe(dev);
}
static int pwm_backlight_ofdata_to_platdata(struct udevice *dev)
{
struct pwm_backlight_priv *priv = dev_get_priv(dev);
struct fdtdec_phandle_args args;
const void *blob = gd->fdt_blob;
int node = dev->of_offset;
int index, ret, count, len;
const u32 *cell;
ret = uclass_get_device_by_phandle(UCLASS_REGULATOR, dev,
"power-supply", &priv->reg);
if (ret) {
debug("%s: Cannot get power supply: ret=%d\n", __func__, ret);
return ret;
}
ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable,
GPIOD_IS_OUT);
if (ret) {
debug("%s: Warning: cannot get enable GPIO: ret=%d\n",
__func__, ret);
if (ret != -ENOENT)
return ret;
}
ret = fdtdec_parse_phandle_with_args(blob, node, "pwms", "#pwm-cells",
0, 0, &args);
if (ret) {
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
ret = uclass_get_device_by_of_offset(UCLASS_PWM, args.node, &priv->pwm);
if (ret) {
debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
return ret;
}
priv->channel = args.args[0];
priv->period_ns = args.args[1];
index = fdtdec_get_int(blob, node, "default-brightness-level", 255);
cell = fdt_getprop(blob, node, "brightness-levels", &len);
count = len / sizeof(u32);
if (cell && count > index) {
priv->default_level = fdt32_to_cpu(cell[index]);
priv->max_level = fdt32_to_cpu(cell[count - 1]);
} else {
priv->default_level = index;
priv->max_level = 255;
}
return 0;
}
static int utmi_clk_ofdata_to_platdata(struct udevice *dev)
{
struct pmc_platdata *plat = dev_get_platdata(dev);
struct udevice *syscon;
uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
"regmap-sfr", &syscon);
if (syscon)
plat->regmap_sfr = syscon_get_regmap(syscon);
return 0;
}
static int ast2500_ofdata_to_platdata(struct udevice *dev)
{
struct ast2500_reset_priv *priv = dev_get_priv(dev);
int ret;
ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
&priv->wdt);
if (ret) {
debug("%s: can't find WDT for reset controller", __func__);
return ret;
}
return 0;
}
int rk_lvds_probe(struct udevice *dev)
{
struct rk_lvds_priv *priv = dev_get_priv(dev);
int ret;
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
&priv->panel);
if (ret) {
debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
dev->name, ret);
return ret;
}
return 0;
}
static int rockchip_dwmmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
struct dwmci_host *host = &priv->host;
struct udevice *pwr_dev __maybe_unused;
u32 minmax[2];
int ret;
int fifo_depth;
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret < 0)
return ret;
priv->periph = ret;
if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
"clock-freq-min-max", minmax, 2))
return -EINVAL;
fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"fifo-depth", 0);
if (fifo_depth < 0)
return -EINVAL;
host->fifoth_val = MSIZE(0x2) |
RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode"))
host->fifo_mode = true;
#ifdef CONFIG_PWRSEQ
/* Enable power if needed */
ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
&pwr_dev);
if (!ret) {
ret = pwrseq_set_power(pwr_dev, true);
if (ret)
return ret;
}
#endif
ret = add_dwmci(host, minmax[1], minmax[0]);
if (ret)
return ret;
upriv->mmc = host->mmc;
return 0;
}
/* Set up the mux ready for use */
static int i2c_mux_post_probe(struct udevice *mux)
{
struct i2c_mux *priv = dev_get_uclass_priv(mux);
int ret;
debug("%s: %s\n", __func__, mux->name);
priv->selected = -1;
ret = uclass_get_device_by_phandle(UCLASS_I2C, mux, "i2c-parent",
&priv->i2c_bus);
if (ret)
return ret;
debug("%s: bus=%p/%s\n", __func__, priv->i2c_bus, priv->i2c_bus->name);
return 0;
}
static int tegra_sor_ofdata_to_platdata(struct udevice *dev)
{
struct tegra_dc_sor_data *priv = dev_get_priv(dev);
int ret;
priv->base = (void *)dev_read_addr(dev);
priv->pmc_base = (void *)syscon_get_first_range(TEGRA_SYSCON_PMC);
if (IS_ERR(priv->pmc_base))
return PTR_ERR(priv->pmc_base);
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "nvidia,panel",
&priv->panel);
if (ret) {
debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
dev->name, ret);
return ret;
}
return 0;
}
static void *map_syscon_chipselects(struct udevice *bus)
{
#if CONFIG_IS_ENABLED(SYSCON)
struct udevice *syscon;
struct regmap *regmap;
const fdt32_t *cell;
int len, err;
err = uclass_get_device_by_phandle(UCLASS_SYSCON, bus,
"syscon-chipselects", &syscon);
if (err) {
debug("%s: unable to find syscon device (%d)\n", __func__,
err);
return NULL;
}
regmap = syscon_get_regmap(syscon);
if (IS_ERR(regmap)) {
debug("%s: unable to find regmap (%ld)\n", __func__,
PTR_ERR(regmap));
return NULL;
}
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(bus),
"syscon-chipselects", &len);
if (len < 2*sizeof(fdt32_t)) {
debug("%s: offset not available\n", __func__);
return NULL;
}
return fdtdec_get_number(cell + 1, 1) + regmap_get_range(regmap, 0);
#else
fdt_addr_t addr;
addr = devfdt_get_addr_index(bus, 2);
return (addr == FDT_ADDR_T_NONE) ? NULL :
map_physmem(addr, 0, MAP_NOCACHE);
#endif
}
static void *get_reg(struct udevice *dev, const char *name)
{
struct udevice *syscon;
struct regmap *regmap;
const fdt32_t *cell;
int len, err;
void *base;
err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
name, &syscon);
if (err) {
pr_err("unable to find syscon device for %s (%d)\n",
name, err);
return NULL;
}
regmap = syscon_get_regmap(syscon);
if (IS_ERR(regmap)) {
pr_err("unable to find regmap for %s (%ld)\n",
name, PTR_ERR(regmap));
return NULL;
}
cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), name,
&len);
if (len < 2*sizeof(fdt32_t)) {
pr_err("offset not available for %s\n", name);
return NULL;
}
base = regmap_get_range(regmap, 0);
if (!base)
return NULL;
return fdtdec_get_number(cell + 1, 1) + base;
}
int syscon_reboot_probe(struct udevice *dev)
{
struct udevice *syscon;
struct syscon_reboot_priv *priv = dev_get_priv(dev);
int err;
err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
"regmap", &syscon);
if (err) {
pr_err("unable to find syscon device\n");
return err;
}
priv->regmap = syscon_get_regmap(syscon);
if (!priv->regmap) {
pr_err("unable to find regmap\n");
return -ENODEV;
}
priv->offset = dev_read_u32_default(dev, "offset", 0);
priv->mask = dev_read_u32_default(dev, "mask", 0);
return 0;
}
