/* Silently enable / disable audio output */
void uda1380_enable_output(bool enable)
{
if (enable) {
uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_DAC | PON_HP);
} else {
uda1380_write_reg(REG_MUTE, MUTE_MASTER);
uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~PON_DAC);
}
}
/**
* Stop sending samples on the I2S bus
*/
void uda1380_disable_recording(void)
{
uda1380_write_reg(REG_PGA, MUTE_ADC);
sleep(HZ/8);
uda1380_write_reg(REG_I2S, I2S_IFMT_IIS);
uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] & ~(PON_LNA | PON_ADCL | PON_ADCR | PON_PGAL | PON_PGAR));
uda1380_write_reg(REG_0, uda1380_regs[REG_0] & ~EN_ADC);
uda1380_write_reg(REG_ADC, SKIP_DCFIL);
}
/* Nice shutdown of UDA1380 codec */
void uda1380_close(void)
{
/* First enable mute and sleep a while */
uda1380_write_reg(REG_MUTE, MUTE_MASTER);
sleep(HZ/8);
/* Then power off the rest of the chip */
uda1380_write_reg(REG_PWR, 0);
uda1380_write_reg(REG_0, 0); /* Disable codec */
}
/* Change the order of the noise chaper, 5th order is recommended above 32kHz */
void uda1380_set_nsorder(int order)
{
switch(order)
{
case 5:
uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] | MIX_CTL_SEL_NS);
break;
case 3:
default:
uda1380_write_reg(REG_MIX_CTL, uda1380_regs[REG_MIX_CTL] & ~MIX_CTL_SEL_NS);
}
}
/**
* Enable or disable recording monitor (so one can listen to the recording)
*
*/
void uda1380_set_monitor(int enable)
{
if (enable)
{
/* enable channel 2 */
uda1380_write_reg(REG_MIX_VOL, (uda1380_regs[REG_MIX_VOL] & 0x00FF) | MIX_VOL_CH_2(0));
uda1380_write_reg(REG_MUTE, 0);
} else
{
/* mute channel 2 */
uda1380_write_reg(REG_MUTE, MUTE_CH2);
uda1380_write_reg(REG_MIX_VOL, (uda1380_regs[REG_MIX_VOL] & 0x00FF) | MIX_VOL_CH_2(0xff));
}
}
/**
* Mute (mute=1) or enable sound (mute=0)
*
*/
int uda1380_mute(int mute)
{
unsigned int value = uda1380_regs[REG_MUTE];
if (mute)
value = value | MUTE_MASTER;
else
value = value & ~MUTE_MASTER;
return uda1380_write_reg(REG_MUTE, value);
}
void audiohw_mute(bool mute)
{
unsigned int value = uda1380_regs[REG_MUTE];
if (mute)
value = value | MUTE_MASTER;
else
value = value & ~MUTE_MASTER;
uda1380_write_reg(REG_MUTE, value);
}
/**
* Calling this function enables the UDA1380 to send
* sound samples over the I2S bus, which is connected
* to the processor's IIS1 interface.
*
* source_mic: true=record from microphone, false=record from line-in
*/
void uda1380_enable_recording(bool source_mic)
{
uda1380_write_reg(REG_0, uda1380_regs[REG_0] | EN_ADC);
if (source_mic)
{
uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_LNA | PON_ADCL);
uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & VGA_GAIN_MASK) | SEL_LNA | SEL_MIC | EN_DCFIL); /* VGA_GAIN: 0=0 dB, F=30dB */
uda1380_write_reg(REG_PGA, 0);
} else
{
uda1380_write_reg(REG_PWR, uda1380_regs[REG_PWR] | PON_PGAL | PON_ADCL | PON_PGAR | PON_ADCR);
uda1380_write_reg(REG_ADC, EN_DCFIL);
uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA] & PGA_GAIN_MASK) | PGA_GAINL(0) | PGA_GAINR(0)); /* PGA_GAIN: 0=0 dB, F=24dB */
}
sleep(HZ/8);
uda1380_write_reg(REG_I2S, uda1380_regs[REG_I2S] | I2S_MODE_MASTER);
uda1380_write_reg(REG_MIX_CTL, MIX_MODE(3)); /* Not sure which mode is the best one.. */
}
/* Returns 0 if successful or -1 if some register failed */
int uda1380_set_regs(void)
{
int i;
memset(uda1380_regs, 0, sizeof(uda1380_regs));
/* Initialize all registers */
for (i=0; i<NUM_DEFAULT_REGS; i++)
{
unsigned char reg = uda1380_defaults[i*2+0];
unsigned short value = uda1380_defaults[i*2+1];
if (uda1380_write_reg(reg, value) == -1)
return -1;
}
return 0;
}
/**
* Sets mixer volume for both channels (0(max) to 228(muted))
*/
int uda1380_set_mixer_vol(int channel1, int channel2)
{
return uda1380_write_reg(REG_MIX_VOL,
MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2));
}
/**
* Sets left and right master volume (0(max) to 252(muted))
*/
int uda1380_set_master_vol(int vol_l, int vol_r)
{
return uda1380_write_reg(REG_MASTER_VOL,
MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
}
/**
* Set recording gain and volume
*
* mic_gain : range 0 .. 15 -> 0 .. 30 dB gain
* linein_gain : range 0 .. 15 -> 0 .. 24 dB gain
*
* adc_volume : range -127 .. 48 -> -63 .. 24 dB gain
* note that 0 -> 0 dB gain..
*/
void uda1380_set_recvol(int mic_gain, int linein_gain, int adc_volume)
{
uda1380_write_reg(REG_DEC_VOL, DEC_VOLL(adc_volume) | DEC_VOLR(adc_volume));
uda1380_write_reg(REG_PGA, (uda1380_regs[REG_PGA] & ~PGA_GAIN_MASK) | PGA_GAINL(linein_gain) | PGA_GAINR(linein_gain));
uda1380_write_reg(REG_ADC, (uda1380_regs[REG_ADC] & ~VGA_GAIN_MASK) | VGA_GAIN(mic_gain));
}
/**
* Sets the treble value (0-3)
*/
void uda1380_set_treble(int value)
{
uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~TREBLE_MASK) | TREBLEL(value) | TREBLER(value));
}
/**
* Sets the bass value (0-12)
*/
void uda1380_set_bass(int value)
{
uda1380_write_reg(REG_EQ, (uda1380_regs[REG_EQ] & ~BASS_MASK) | BASSL(value) | BASSR(value));
}
/**
* Sets mixer volume for both channels (0(max) to 228(muted))
*/
void audiohw_set_mixer_vol(int channel1, int channel2)
{
uda1380_write_reg(REG_MIX_VOL,
MIX_VOL_CH_1(channel1) | MIX_VOL_CH_2(channel2));
}
/**
* Sets left and right master volume (0(max) to 252(muted))
*/
void audiohw_set_master_vol(int vol_l, int vol_r)
{
uda1380_write_reg(REG_MASTER_VOL,
MASTER_VOL_LEFT(vol_l) | MASTER_VOL_RIGHT(vol_r));
}
