static void udd_ep_trans_done(udd_ep_id_t ep)
{
uint32_t udd_dma_ctrl = 0;
udd_ep_job_t *ptr_job;
iram_size_t next_trans;
irqflags_t flags;
// Get job corresponding at endpoint
ptr_job = &udd_ep_job[ep - 1];
if (!ptr_job->busy) {
return; // No job is running, then ignore it (system error)
}
if (ptr_job->nb_trans != ptr_job->buf_size) {
// Need to send or receive other data
next_trans = ptr_job->buf_size - ptr_job->nb_trans;
if (UDD_ENDPOINT_MAX_TRANS < next_trans) {
// The USB hardware support a maximum
// transfer size of UDD_ENDPOINT_MAX_TRANS Bytes
next_trans = UDD_ENDPOINT_MAX_TRANS;
// Set 0 to transfer the maximum
udd_dma_ctrl = (0 <<
AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_OFFSET)
& AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_MASK;
} else {
udd_dma_ctrl = (next_trans <<
AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_OFFSET)
& AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_MASK;
}
if (Is_udd_endpoint_in(ep)) {
if (0 != next_trans % udd_get_endpoint_size(ep)) {
// Enable short packet option
// else the DMA transfer is accepted
// and interrupt DMA valid but nothing is sent.
udd_dma_ctrl |= AVR32_USBB_UDDMA1_CONTROL_DMAEND_EN_MASK;
// No need to request another ZLP
ptr_job->b_shortpacket = false;
}
} else {
if ((USB_EP_TYPE_ISOCHRONOUS != udd_get_endpoint_type(ep))
|| (next_trans <= udd_get_endpoint_size(ep))) {
// Enable short packet reception
udd_dma_ctrl |= AVR32_USBB_UDDMA1_CONTROL_EOT_IRQ_EN_MASK
| AVR32_USBB_UDDMA1_CONTROL_BUFF_CLOSE_IN_EN_MASK;
}
}
// Start USB DMA to fill or read fifo of the selected endpoint
udd_endpoint_dma_set_addr(ep, (U32) &ptr_job->buf[ptr_job->nb_trans]);
udd_dma_ctrl |= AVR32_USBB_UDDMA1_CONTROL_EOBUFF_IRQ_EN_MASK |
AVR32_USBB_UDDMA1_CONTROL_CH_EN_MASK;
// Disable IRQs to have a short sequence
// between read of EOT_STA and DMA enable
flags = cpu_irq_save();
if ( !(udd_endpoint_dma_get_status(ep)
& AVR32_USBB_UDDMA1_STATUS_EOT_STA_MASK)) {
udd_endpoint_dma_set_control(ep, udd_dma_ctrl);
ptr_job->nb_trans += next_trans;
udd_enable_endpoint_dma_interrupt(ep);
cpu_irq_restore(flags);
return;
}
cpu_irq_restore(flags);
// Here a ZLP has been received
// and the DMA transfer must be not started.
// It is the end of transfer
ptr_job->buf_size = ptr_job->nb_trans;
}
if (Is_udd_endpoint_in(ep)) {
if (ptr_job->b_shortpacket) {
// Need to send a ZLP (No possible with USB DMA)
// enable interrupt to wait a free bank to sent ZLP
udd_ack_in_send(ep);
if (Is_udd_write_enabled(ep)) {
// Force interrupt in case of ep already free
udd_raise_in_send(ep);
}
udd_enable_in_send_interrupt(ep);
udd_enable_endpoint_interrupt(ep);
return;
}
}
// Call callback to signal end of transfer
udd_ep_finish_job(ptr_job, false, ep);
}
bool udd_ep_run(udd_ep_id_t ep, bool b_shortpacket,
uint8_t * buf, iram_size_t buf_size,
udd_callback_trans_t callback)
{
bool b_dir_in;
uint32_t udd_dma_ctrl = 0;
udd_ep_job_t *ptr_job;
irqflags_t flags;
b_dir_in = (USB_EP_DIR_IN == (ep & USB_EP_DIR_IN));
ep &= USB_EP_ADDR_MASK;
if (USB_DEVICE_MAX_EP < ep)
return false;
// Get job about endpoint
ptr_job = &udd_ep_job[ep - 1];
if ((!Is_udd_endpoint_enabled(ep))
|| Is_udd_endpoint_stall_requested(ep)
|| ptr_job->stall_requested)
return false; // Endpoint is halted
flags = cpu_irq_save();
if (ptr_job->busy == true) {
cpu_irq_restore(flags);
return false; // Job already on going
}
ptr_job->busy = true;
cpu_irq_restore(flags);
// The USBB supports a maximum transfer size of 64KB
if (0x10000 <= buf_size) {
// Transfer size = 64KB
ptr_job->buf_size = 0x10000;
buf_size = 0;
} else {
ptr_job->buf_size = buf_size;
if (b_dir_in && (0 != buf_size % udd_get_endpoint_size(ep))) {
// Force short packet option to send a shortpacket on IN,
// else the DMA transfer is accepted and interrupt DMA valid but nothing is sent.
b_shortpacket = true;
}
}
ptr_job->buf = buf;
ptr_job->call_trans = callback;
// Start USB DMA to fill or read fifo of the selected endpoint
udd_endpoint_dma_set_addr(ep, (U32) buf);
if (b_shortpacket) {
if (b_dir_in) {
udd_dma_ctrl = AVR32_USBB_UDDMA1_CONTROL_DMAEND_EN_MASK;
} else {
udd_dma_ctrl = AVR32_USBB_UDDMA1_CONTROL_EOT_IRQ_EN_MASK
|
AVR32_USBB_UDDMA1_CONTROL_BUFF_CLOSE_IN_EN_MASK;
}
}
udd_dma_ctrl |= (buf_size <<
AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_OFFSET)
& AVR32_USBB_UDDMA1_CONTROL_CH_BYTE_LENGTH_MASK;
udd_dma_ctrl |= AVR32_USBB_UDDMA1_CONTROL_EOBUFF_IRQ_EN_MASK |
AVR32_USBB_UDDMA1_CONTROL_CH_EN_MASK;
udd_enable_endpoint_bank_autoswitch(ep);
udd_endpoint_dma_set_control(ep, udd_dma_ctrl);
flags = cpu_irq_save();
udd_enable_endpoint_dma_interrupt(ep);
cpu_irq_restore(flags);
return true;
}
