static void up_setupmappings(void)
{
int i, j;
for (i = 0; i < NMAPPINGS; i++)
{
uint32_t sect_paddr = g_section_mapping[i].physbase;
uint32_t sect_vaddr = g_section_mapping[i].virtbase;
uint32_t mmuflags = g_section_mapping[i].mmuflags;
for (j = 0; j < g_section_mapping[i].nsections; j++)
{
up_setlevel1entry(sect_paddr, sect_vaddr, mmuflags);
sect_paddr += SECTION_SIZE;
sect_vaddr += SECTION_SIZE;
}
}
}
static void up_vectormapping(void)
{
uint32_t vector_paddr = DM320_IRAM_PADDR;
uint32_t vector_vaddr = DM320_VECTOR_VADDR;
uint32_t end_paddr = vector_paddr + DM320_IRAM_SIZE;
/* We want to keep our interrupt vectors and interrupt-related logic in zero-wait
* state internal RAM (IRAM). The DM320 has 16Kb of IRAM positioned at physical
* address 0x0000:0000; we need to map this to 0xffff:0000.
*/
while (vector_paddr < end_paddr)
{
up_setlevel2coarseentry(PGTABLE_L2_COARSE_VBASE, vector_paddr, vector_vaddr,
MMU_L2_VECTORFLAGS);
vector_paddr += 4096;
vector_vaddr += 4096;
}
/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
up_setlevel1entry(PGTABLE_L2_COARSE_PBASE, DM320_VECTOR_VCOARSE, MMU_L1_VECTORFLAGS);
}
