/* * シリアルI/Oポートのオープン */ SIOPCB * upd72001_opn_por(ID siopid, VP_INT exinf) { SIOPCB *siopcb; const SIOPINIB *siopinib; siopcb = get_siopcb(siopid); siopinib = siopcb->siopinib; upd72001_write_reg(siopinib->ctrl, CR_RESET); if (!upd72001_openflag()) { upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA, UPD72001_CR2, 0x18); upd72001_write_ctrl((VP) TADR_UPD72001_CTRLB, UPD72001_CR2, 0x00); } siopcb->cr1 = CR1_DOWN; upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR1, siopcb->cr1); upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR4, siopinib->cr4_def); upd72001_write_brg(siopinib->ctrl, UPD72001_CR12, 0x01, siopinib->brg2_def, siopinib->brg1_def); upd72001_write_brg(siopinib->ctrl, UPD72001_CR12, 0x02, siopinib->brg2_def, siopinib->brg1_def); upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR15, CR15_DEF); upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR14, CR14_DEF); upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR10, CR10_DEF); upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR3, siopinib->cr3_def); upd72001_write_ctrl(siopinib->ctrl, UPD72001_CR5, siopinib->cr5_def); siopcb->exinf = exinf; siopcb->getready = siopcb->putready = FALSE; siopcb->openflag = TRUE; return(siopcb); }
/* * シリアルI/Oポートのオープン */ SIOPCB * upd72001_opn_por(ID siopid, intptr_t exinf) { SIOPCB *p_siopcb; const SIOPINIB *p_siopinib; p_siopcb = get_siopcb(siopid); p_siopinib = p_siopcb->p_siopinib; upd72001_write_reg(p_siopinib->ctrl, CR_RESET); if (!upd72001_openflag()) { upd72001_write_ctrl((void *) TADR_UPD72001_CTRLA, UPD72001_CR2, 0x18); upd72001_write_ctrl((void *) TADR_UPD72001_CTRLB, UPD72001_CR2, 0x00); } p_siopcb->cr1 = CR1_DOWN; upd72001_write_ctrl(p_siopinib->ctrl, UPD72001_CR1, p_siopcb->cr1); upd72001_write_ctrl(p_siopinib->ctrl, UPD72001_CR4, p_siopinib->cr4_def); upd72001_write_brg(p_siopinib->ctrl, UPD72001_CR12, 0x01U, p_siopinib->brg2_def, p_siopinib->brg1_def); upd72001_write_brg(p_siopinib->ctrl, UPD72001_CR12, 0x02U, p_siopinib->brg2_def, p_siopinib->brg1_def); upd72001_write_ctrl(p_siopinib->ctrl, UPD72001_CR15, CR15_DEF); upd72001_write_ctrl(p_siopinib->ctrl, UPD72001_CR14, CR14_DEF); upd72001_write_ctrl(p_siopinib->ctrl, UPD72001_CR10, CR10_DEF); upd72001_write_ctrl(p_siopinib->ctrl, UPD72001_CR3, p_siopinib->cr3_def); upd72001_write_ctrl(p_siopinib->ctrl, UPD72001_CR5, p_siopinib->cr5_def); p_siopcb->exinf = exinf; p_siopcb->getready = false; p_siopcb->putready = false; p_siopcb->openflag = true; return(p_siopcb); }
/* * シリアルI/Oポートからのコールバックの禁止 */ void upd72001_dis_cbr(SIOPCB *siopcb, UINT cbrtn) { UB cr1_bit = 0; switch (cbrtn) { case SIO_ERDY_SND: cr1_bit = CR1_SEND; break; case SIO_ERDY_RCV: cr1_bit = CR1_RECV; break; } siopcb->cr1 &= ~cr1_bit; upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, siopcb->cr1); }
/* * シリアルI/Oポートからのコールバックの禁止 */ void upd72001_dis_cbr(SIOPCB *p_siopcb, uint_t cbrtn) { uint8_t cr1_bit; switch (cbrtn) { case SIO_RDY_SND: cr1_bit = CR1_SEND; break; case SIO_RDY_RCV: cr1_bit = CR1_RECV; break; default: cr1_bit = 0U; break; } p_siopcb->cr1 &= ~cr1_bit; upd72001_write_ctrl(p_siopcb->p_siopinib->ctrl, UPD72001_CR1, p_siopcb->cr1); }
/* * シリアルI/Oポートのクローズ */ void upd72001_cls_por(SIOPCB *siopcb) { upd72001_write_ctrl(siopcb->siopinib->ctrl, UPD72001_CR1, CR1_DOWN); siopcb->openflag = FALSE; }
/* * EOI(End Of Interrupt)発行 */ Inline void upd72001_eoi() { upd72001_write_ctrl((VP) TADR_UPD72001_CTRLA, UPD72001_CR0, CR0_EOI); }
/* * シリアルI/Oポートのクローズ */ void upd72001_cls_por(SIOPCB *p_siopcb) { upd72001_write_ctrl(p_siopcb->p_siopinib->ctrl, UPD72001_CR1, CR1_DOWN); p_siopcb->openflag = false; }