int dram_init(void)
{
static const struct fsl_mmdc_info mparam = {
0x05180000, /* mdctl */
0x00030035, /* mdpdc */
0x12554000, /* mdotc */
0xbabf7954, /* mdcfg0 */
0xdb328f64, /* mdcfg1 */
0x01ff00db, /* mdcfg2 */
0x00001680, /* mdmisc */
0x0f3c8000, /* mdref */
0x00002000, /* mdrwd */
0x00bf1023, /* mdor */
0x0000003f, /* mdasp */
0x0000022a, /* mpodtctrl */
0xa1390003, /* mpzqhwctrl */
};
mmdc_init(&mparam);
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}
int dram_init(void)
{
/*
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}
int dram_init(void)
{
#ifdef CONFIG_TARGET_LS1012AFRWY
int board_rev;
#endif
struct fsl_mmdc_info mparam = {
0x04180000, /* mdctl */
0x00030035, /* mdpdc */
0x12554000, /* mdotc */
0xbabf7954, /* mdcfg0 */
0xdb328f64, /* mdcfg1 */
0x01ff00db, /* mdcfg2 */
0x00001680, /* mdmisc */
0x0f3c8000, /* mdref */
0x00002000, /* mdrwd */
0x00bf1023, /* mdor */
0x0000003f, /* mdasp */
0x0000022a, /* mpodtctrl */
0xa1390003, /* mpzqhwctrl */
};
#ifdef CONFIG_TARGET_LS1012AFRWY
board_rev = get_board_version();
if (board_rev == BOARD_REV_C) {
mparam.mdctl = 0x05180000;
gd->ram_size = SYS_SDRAM_SIZE_1024;
} else {
gd->ram_size = SYS_SDRAM_SIZE_512;
}
#else
gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
#endif
mmdc_init(&mparam);
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}