void hal_uart_dma_receive_block(uint8_t *data, uint16_t size){
// hal_uart_manual_rts_clear();
gpio_clear(GPIOB, GPIO_DEBUG_1);
/*
* USART3_RX is on DMA_CHANNEL3
*/
// printf("hal_uart_dma_receive_block req size %u\n", size);
/* Reset DMA channel*/
dma_channel_reset(DMA1, DMA_CHANNEL3);
dma_set_peripheral_address(DMA1, DMA_CHANNEL3, (uint32_t)&USART3_DR);
dma_set_memory_address(DMA1, DMA_CHANNEL3, (uint32_t)data);
dma_set_number_of_data(DMA1, DMA_CHANNEL3, size);
dma_set_read_from_peripheral(DMA1, DMA_CHANNEL3);
dma_enable_memory_increment_mode(DMA1, DMA_CHANNEL3);
dma_set_peripheral_size(DMA1, DMA_CHANNEL3, DMA_CCR_PSIZE_8BIT);
dma_set_memory_size(DMA1, DMA_CHANNEL3, DMA_CCR_MSIZE_8BIT);
dma_set_priority(DMA1, DMA_CHANNEL3, DMA_CCR_PL_HIGH);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL3);
dma_enable_channel(DMA1, DMA_CHANNEL3);
usart_enable_rx_dma(USART3);
}
void dma_request(void* buffer, const int datasize)
{
dma_set_memory_address(DMA1, DMA_CHANNEL5, (uint32_t) buffer);
dma_set_number_of_data(DMA1, DMA_CHANNEL5, datasize);
dma_enable_channel(DMA1, DMA_CHANNEL5);
signal_host();
usart_enable_rx_dma(USART2);
}
/** Setup the USART for recieve with DMA. This function sets up the DMA
* controller and additional USART parameters for DMA receive. The USART must
* first be configured using \ref usart_setup_common. */
void usart_rx_dma_setup(void) {
/* Set up the USART1 RX DMA and interrupts. */
/* Enable clock to DMA peripheral. */
RCC_AHB1ENR |= RCC_AHB1ENR_DMA2EN;
/* Enable RX DMA on the USART. */
usart_enable_rx_dma(USART1);
/* USART1 RX - DMA2, stream 5, channel 4. */
/* Make sure stream is disabled to start. */
DMA2_S5CR &= ~DMA_SxCR_EN;
DMA2_S5CR = 0;
/* Configure the DMA controller. */
/* Error interrupts. */
DMA2_S5CR = DMA_SxCR_DMEIE | DMA_SxCR_TEIE |
/* Transfer complete interrupt. */
DMA_SxCR_TCIE |
/* Enable circular buffer mode. */
DMA_SxCR_CIRC |
DMA_SxCR_DIR_PERIPHERAL_TO_MEM |
/* Increment the memory address after each transfer. */
DMA_SxCR_MINC |
/* 8 bit transfers from USART peripheral. */
DMA_SxCR_PSIZE_8BIT |
/* and to memory. */
DMA_SxCR_MSIZE_8BIT |
/* Low priority. */
DMA_SxCR_PL_LOW |
/* The channel selects which request line will trigger a
* transfer. In this case, channel 4 = UART1_RX
* (see CD00225773.pdf Table 23). */
DMA_SxCR_CHSEL(4);
/* Transfer up the the length of the buffer. */
DMA2_S5NDTR = USART_RX_BUFFER_LEN;
DMA2_S5PAR = &USART1_DR; /* DMA from the USART1 data register. */
DMA2_S5M0AR = rx_buff; /* to the rx_buff. */
// TODO: Investigate more about the best FIFO settings.
DMA2_S5FCR = DMA_SxFCR_DMDIS | /* Enable DMA stream FIFO. */
DMA_SxFCR_FTH_2_4_FULL | /* Trigger level 1/2 full. */
DMA_SxFCR_FEIE; /* Enable FIFO error interrupt. */
rx_rd = 0; /* Buffer is empty to begin with. */
rd_wraps = wr_wraps = 0;
/* Enable DMA2 Stream 5 (RX) interrupts with the NVIC. */
nvic_enable_irq(NVIC_DMA2_STREAM5_IRQ);
/* Enable the DMA channel. */
DMA2_S5CR |= DMA_SxCR_EN;
}
/** Setup the USART for receive with DMA.
* This function sets up the DMA controller and additional USART parameters for
* DMA receive. The USART must already be configured for normal operation.
*
* \param s The USART DMA state structure.
* \oaram usart The USART base address.
* \param dma The DMA controller base address.
* \param stream The DMA stream number to use.
* \param channel The DMA channel to use. The stream and channel must
* correspond to a USART RX channel.
*/
void usart_rx_dma_setup(usart_rx_dma_state* s, u32 usart,
u32 dma, u8 stream, u8 channel)
{
s->dma = dma;
s->usart = usart;
s->stream = stream;
s->channel = channel;
chBSemInit(&s->ready_sem, TRUE);
s->byte_counter = 0;
s->last_byte_ticks = chTimeNow();
/* Enable clock to DMA peripheral. */
if (dma == DMA1)
RCC_AHB1ENR |= RCC_AHB1ENR_DMA1EN;
else if (dma == DMA2)
RCC_AHB1ENR |= RCC_AHB1ENR_DMA2EN;
/* Enable RX DMA on the USART. */
usart_enable_rx_dma(usart);
/* Make sure stream is disabled to start. */
DMA_SCR(dma, stream) &= ~DMA_SxCR_EN;
/* RM0090 - 9.3.17 : Supposed to wait until enable bit reads '0' before we
* write to registers. */
while (DMA_SCR(dma, stream) & DMA_SxCR_EN) ;
/* RM0090 - 9.3.17 : Supposed to clear any interrupts in DMA status register
* before we reconfigure registers. */
dma_clear_interrupt_flags(dma, stream, DMA_ISR_FLAGS);
/* Configure the DMA controller. */
DMA_SCR(dma, stream) = 0;
DMA_SCR(dma, stream) =
/* Error interrupts. */
DMA_SxCR_DMEIE | DMA_SxCR_TEIE |
/* Transfer complete interrupt. */
DMA_SxCR_TCIE |
/* Enable circular buffer mode. */
DMA_SxCR_CIRC |
DMA_SxCR_DIR_PERIPHERAL_TO_MEM |
/* Increment the memory address after each transfer. */
DMA_SxCR_MINC |
/* 8 bit transfers from USART peripheral. */
DMA_SxCR_PSIZE_8BIT |
/* and to memory. */
DMA_SxCR_MSIZE_8BIT |
/* Low priority. */
DMA_SxCR_PL_LOW |
/* The channel selects which request line will trigger a transfer.
* (see CD00225773.pdf Table 23). */
DMA_SxCR_CHSEL(channel);
/* Transfer up to the length of the buffer. */
DMA_SNDTR(dma, stream) = USART_RX_BUFFER_LEN;
/* DMA from the USART data register... */
DMA_SPAR(dma, stream) = &USART_DR(usart);
/* ...to the RX buffer. */
DMA_SM0AR(dma, stream) = s->buff;
/* Buffer is empty to begin with. */
s->rd = 0;
s->rd_wraps = s->wr_wraps = 0;
/* Enable DMA interrupts for this stream with the NVIC. */
if (dma == DMA1)
nvicEnableVector(dma_irq_lookup[0][stream],
CORTEX_PRIORITY_MASK(USART_DMA_ISR_PRIORITY));
else if (dma == DMA2)
nvicEnableVector(dma_irq_lookup[1][stream],
CORTEX_PRIORITY_MASK(USART_DMA_ISR_PRIORITY));
/* These reads clear error flags before enabling DMA */
(void)USART_SR(usart);
(void)USART_DR(usart);
/* Enable the DMA channel. */
DMA_SCR(dma, stream) |= DMA_SxCR_EN;
}
