/************************************************************************* * FUNCTION * DclPMU_Control * * DESCRIPTION * This function is to send command to control the PMU module. * * PARAMETERS * handle: The handle value returned from DclPMU_Open * cmd: a control command for PMU module * PMU38: Refer dcl_pmu38.c * * * data: The data of the control command * PMU38: Refer dcl_pmu38.c * * * RETURNS * STATUS_OK: command is executed successfully. * STATUS_FAIL: command is failed. * STATUS_INVALID_CMD: It's a invalid command. * *************************************************************************/ DCL_STATUS DclPMU_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data) { #ifndef PMIC_PRESENT return STATUS_OK; // For PMIC = NONE #else #if defined(DCL_PMIC_ACCESS_TIME_LOG) DCL_STATUS pmu_control_status; pmic_access_duration_log[PMIC_DCL_DBG][pmic_access_duration_index].start_time = ust_get_current_time(); pmu_control_status = pmu_control_handler(handle,cmd,data); pmic_access_duration_log[PMIC_DCL_DBG][pmic_access_duration_index].end_time = ust_get_current_time(); pmic_access_duration_log[PMIC_DCL_DBG][pmic_access_duration_index].cmd = cmd; pmic_access_duration_log[PMIC_DCL_DBG][pmic_access_duration_index].duration_time = ust_get_duration(pmic_access_duration_log[PMIC_DCL_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_DCL_DBG][pmic_access_duration_index].end_time); if(pmic_access_duration_log[PMIC_DCL_DBG][pmic_access_duration_index].duration_time > PMIC_ACCESS_DURATION_THRESHOLD) { pmic_access_timing_issue_log[pmic_access_timing_issue_index] = pmic_access_duration_index; pmic_access_timing_issue_index++; pmic_access_timing_issue_index = pmic_access_timing_issue_index&(MAX_PMIC_DURATION_INFO_SIZE - 1); } pmic_access_duration_index++; pmic_access_duration_index = pmic_access_duration_index&(MAX_PMIC_DURATION_INFO_SIZE - 1); return pmu_control_status; #else return pmu_control_handler(handle,cmd,data); #endif // End of #if defined(DCL_PMIC_ACCESS_TIME_LOG) #endif //return STATUS_INVALID_CMD; }
static void AUDIO_DELAY(uint16 delay) { kal_uint32 curr_frc, latest_us; curr_frc = ust_get_current_time();//unit: micro second (us) do{ latest_us = ust_get_current_time();; }while(delay > ust_get_duration(curr_frc, latest_us)); }
/************************************************************************* * FUNCTION * USC_Get_TimeStamp * * DESCRIPTION * This function calculate the frame number. * * PARAMETERS * none * * RETURNS * Frame number since system power up * *************************************************************************/ kal_uint32 DEVDRV_LS_INTSRAM_ROCODE USC_Get_TimeStamp( void ) { #if defined(__ALIGN_2G_CLOCK__) kal_uint32 uscnti,curFrame,_savedMask; _savedMask = SaveAndSetIRQMask(); uscnti= ust_get_current_time(); if (uscnti >= Pre_USCNTI) { curFrame = USCNT_TO_FRAME( uscnti - Pre_USCNTI ); // dur/3250/(120/26) } else { curFrame = USCNT_TO_FRAME((USCNT_WRAP - Pre_USCNTI) + uscnti); } FrameCount += curFrame; Pre_USCNTI += FRAME_TO_USCNT(curFrame); if( Pre_USCNTI > USCNT_WRAP ) { Pre_USCNTI -= USCNT_WRAP; } RestoreIRQMask(_savedMask); return FrameCount; #else kal_uint32 uscnti,curFrame,_savedMask; _savedMask = SaveAndSetIRQMask(); #if defined(__HW_OSTICK_CNT__) HW_WRITE(OST_CMD, CMD_MAGIC_VALUE | 0x02); curFrame = HW_READ(OST_TIMER_CNT_R); #else uscnti= ust_get_current_time(); if (uscnti >= Pre_USCNTI) { Total_USCNTI += (uscnti - Pre_USCNTI); } else { Total_USCNTI += ((USCNT_WRAP - Pre_USCNTI) + uscnti); } Pre_USCNTI = uscnti; curFrame = USCNT_TO_FRAME(Total_USCNTI); #endif RestoreIRQMask(_savedMask); return curFrame; #endif }
/*----------------------------------------------------------------------- * FUNCTION * GPTCB_10MS_HISR * * DESCRIPTION * GPT Callback HISR : 10ms * * CALLS * * PARAMETERS * void * * RETURNS * None * * GLOBALS AFFECTED * external_global *------------------------------------------------------------------------*/ DEVDRV_LS_INTSRAM_ROCODE void GPTCB_10MS_HISR(void) { kal_uint8 index; kal_uint32 savedMask; kal_uint32 checkMask = 0xFFFFFFFF; IFDEF_GPT_TRACE(kal_uint32 time1); IFDEF_GPT_TRACE(kal_uint32 time2); gptCB_ticks++; // Bit matched method to check if a GPT items is activated // Search whole GPT items for (index = 0; (index < MAX_GPT_ITEMS)&&(gptCB_status&checkMask); index++) { savedMask = SaveAndSetIRQMask(); if( (gptCB_status & (1 << index)) && (gptCB_ticks >= gptCB_items[index].tick) ) { gptCB_status &= ~(1<<index); RestoreIRQMask(savedMask); IFDEF_GPT_TRACE(time1 = ust_get_current_time()); #if defined(__CR4__) IFDEF_GPT_CB_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(gpt_cb_enter_time[index])); #elif defined(__MTK_MMU_V2__) /* __CR4__ */ IFDEF_GPT_CB_MEASURE_TIME(gpt_cb_enter_time[index]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE()); #endif /* __MTK_MMU_V2__ */ gptCB_items[index].gptimer_func(gptCB_items[index].parameter); #if defined(__CR4__) IFDEF_GPT_CB_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(gpt_cb_leave_time[index])); #elif defined(__MTK_MMU_V2__) /* __CR4__ */ IFDEF_GPT_CB_MEASURE_TIME(gpt_cb_leave_time[index]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE()); #endif /* __MTK_MMU_V2__ */ IFDEF_GPT_TRACE(time2 = ust_get_current_time()); GPT_DBG(index, time1, time2); } else { RestoreIRQMask(savedMask); } checkMask ^= (1 << index); } savedMask = SaveAndSetIRQMask(); if (gptCB_status == 0) { // UT Test road test. gptCB_ticks = 0; drv_gpt_stop_timer(DRV_GPT_CALLBACK_TIMER); DCL_GPT_BUS_CLOCK_TRY_OFF(); } RestoreIRQMask(savedMask); }
__SECTION__(INTSRAM_ROCODE) unsigned int dcm_ts_log(int idx) { static unsigned int gsn; unsigned int usc; if (idx==0) gsn++; if (gsn != dcm_ts_log_data[idx].sn) { usc = ust_get_current_time(); dcm_ts_log_data[idx].usc = usc; dcm_ts_log_data[idx].sn = gsn; return usc; } return (unsigned int)-1; }
/************************************************************************* * FUNCTION * isrC_Main * * DESCRIPTION * This function implement IRQ's LISR main dispatch routine * * CALLS * * CALL BY * INT_IRQ_Parse() * * PARAMETERS * * RETURNS * *************************************************************************/ #if !defined(__SSDVT_TEST__) #if defined(MT6290) && defined(__ARM7EJ_S__) void DEVDRV_LS_COPRO_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx) #else /* defined(MT6290) && defined(__ARM7EJ_S__) */ void DEVDRV_LS_INTSRAM_ROCODE isrC_Main(kal_uint32 irqx) #endif /* else of "defined(MT6290) && defined(__ARM7EJ_S__)" */ { #if defined(__UNIFIED_ISR_LEVEL__) // kal_hisr processing_ehisrid; kal_hisrid processing_hisrid; #else /* __UNIFIED_ISR_LEVEL__ */ void *processing_lisr_backup; kal_uint16 processing_irqx_backup; processing_lisr_backup = processing_lisr; processing_irqx_backup = processing_irqx; #endif /* __UNIFIED_ISR_LEVEL__ */ processing_irqx = irqx; processing_lisr = (void*)lisr_dispatch_tbl[irqx].lisr_handler; processing_irqCnt++; #if defined __MALMO_ASM_SWTR__ ST_MALMO_ASM_ChangeContextID(); #endif /* __MALMO_ASM_SWTR */ if (KAL_FALSE == SLA_IsLmuLogging()) { LMU_Write_ISR_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx)); } if (SA_LoggingIndex != 0) { SLA_LoggingLISR(0xaaaa0000 | ((kal_uint32)processing_irqx)); } CPU_SET_CONTEXT_ID(0xaaaa0000 | ((kal_uint32)processing_irqx)); #ifdef __SWDBG_SUPPORT__ *SWDBG_MPCON = ((irqx + 0x100) << 16) | 0x8000; #endif /* __SWDBG_SUPPORT__ */ #ifdef __WAKEUP_IRQ_DEBUG__ if (wkup_intr_log_indx != WKUP_LOG_BUF_MAX) { wkup_intr_log_buf[wkup_intr_log_indx].irq = processing_irqx; wkup_intr_log_indx++; if (wkup_intr_log_indx == WKUP_LOG_BUF_MAX) { wkup_intr_log_indx = 0; } } if (wkup_timer_log_indx != WKUP_LOG_BUF_MAX) { if (wake_tm_name != NULL) { wkup_timer_log_buf[wkup_timer_log_indx].timer_name = wake_tm_name; wake_tm_name = NULL; wkup_timer_log_indx++; if (wkup_timer_log_indx == WKUP_LOG_BUF_MAX) { wkup_timer_log_indx = 0; } } } #endif /* __WAKEUP_IRQ_DEBUG__ */ #if defined(DEBUG_KAL) && defined(DEBUG_TIMER) && defined(__CR4__) if(TimerHISR_State == 1) { GET_CURRENT_TIME(TimerHISR_Exclude_Start_Time); TimerHISR_State = 2; } #endif #if defined(__TP_SUPPORT_TIMING_CHECK__) if(Thread_Protect_State==1) { Thread_Protect_State=2; TP_Exclude_Start_Time = ust_get_current_time(); } #endif #ifdef __DEMAND_PAGING_PERFORMANCE_PROFILING__ demp_preempt_time_start(); #endif #if defined(__UNIFIED_ISR_LEVEL__) // processing_ehisrid = intrID2hisrEID[irqx]; // ASSERT(0xFF != processing_ehisrid); // processing_hisrid = hisrid_g[processing_ehisrid]; processing_hisrid = intrID2hisrID[irqx]; if(processing_hisrid != drv_hisr) { EXT_ASSERT(NULL != processing_hisrid, irqx, processing_irqCnt, (kal_uint32)processing_lisr); kal_activate_hisr(processing_hisrid); } else { drv_active_hisr(irqx); } /* no nested interrupt */ processing_lisr = NULL; processing_irqx = IRQ_NOT_LISR_CONTEXT; #else /* __UNIFIED_ISR_LEVEL__ */ ReEnableIRQ(); #if defined(__CR4__) IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_enter_time[irqx])); #elif defined(__MTK_MMU_V2__) IFDEF_LISR_MEASURE_TIME(lisr_enter_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE()); #endif lisr_dispatch_tbl[irqx].lisr_handler(irqx); #if defined(__CR4__) IFDEF_LISR_MEASURE_TIME(CP15_PMU_GET_CYCLE_CNT(lisr_leave_time[irqx])); #elif defined(__MTK_MMU_V2__) IFDEF_LISR_MEASURE_TIME(lisr_leave_time[irqx]=CACHE_FREE_RUN_CYCLE_COUNTER_GET_CYCLE()); #endif DisableIRQ(); processing_irqx = processing_irqx_backup; processing_lisr = processing_lisr_backup; #endif /* __UNIFIED_ISR_LEVEL__ */ if (KAL_FALSE == SLA_IsLmuLogging()) { LMU_Write_ISR_END_CSM(0xaaaaaaaa); } if (SA_LoggingIndex != 0) { SLA_LoggingLISR(0xaaaaaaaa); } CPU_SET_CONTEXT_ID(0xaaaaaaaa); #if defined __MALMO_ASM_SWTR__ ST_MALMO_ASM_ChangeContextID(); #endif /* __MALMO_ASM_SWTR */ /* Binary-coded IRQ idx */ SYS_endIsr((kal_uint8)irqx); }
void isrC_Main(void) { kal_uint32 irqx; void *processing_lisr_backup; kal_uint16 processing_irqx_backup; irqx = IRQ_Status(); if(irqx== -1) return; processing_lisr_backup = processing_lisr; processing_irqx_backup = processing_irqx; processing_irqx = irqx; processing_lisr = (void*)lisr_dispatch_tbl[irqx].lisr_handler; processing_irqCnt++; #if defined __MALMO_ASM_SWTR__ ST_MALMO_ASM_ChangeContextID(); #endif /* __MALMO_ASM_SWTR */ if (KAL_FALSE == SLA_IsLmuLogging()) { LMU_Write_ISR_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx)); } if (SA_LoggingIndex != 0) { SLA_LoggingLISR(0xaaaa0000 | ((kal_uint32)processing_irqx)); } #ifdef __SWDBG_SUPPORT__ *SWDBG_MPCON = ((irqx + 0x100) << 16) | 0x8000; #endif /* __SWDBG_SUPPORT__ */ #ifdef __WAKEUP_IRQ_DEBUG__ if (wkup_intr_log_indx != WKUP_LOG_BUF_MAX) { wkup_intr_log_buf[wkup_intr_log_indx].irq = processing_irqx; wkup_intr_log_indx++; if (wkup_intr_log_indx == WKUP_LOG_BUF_MAX) { wkup_intr_log_indx = 0; } } if (wkup_timer_log_indx != WKUP_LOG_BUF_MAX) { if (wake_tm_name != NULL) { wkup_timer_log_buf[wkup_timer_log_indx].timer_name = wake_tm_name; wake_tm_name = NULL; wkup_timer_log_indx++; if (wkup_timer_log_indx == WKUP_LOG_BUF_MAX) { wkup_timer_log_indx = 0; } } } #endif /* __WAKEUP_IRQ_DEBUG__ */ #if defined(DEBUG_KAL) && defined(DEBUG_TIMER) && defined(__CR4__) if(TimerHISR_State == 1) { GET_CURRENT_TIME(TimerHISR_Exclude_Start_Time); TimerHISR_State = 2; } #endif #if defined(__TP_SUPPORT_TIMING_CHECK__) if(Thread_Protect_State==1) { Thread_Protect_State=2; TP_Exclude_Start_Time = ust_get_current_time(); } #endif #ifdef __DEMAND_PAGING_PERFORMANCE_PROFILING__ demp_preempt_time_start(); #endif ReEnableIRQ(); lisr_dispatch_tbl[irqx].lisr_handler(); DisableIRQ(); /* restore global variable processing_lisr and processing_irqx to value of preempted IRQ */ processing_irqx = processing_irqx_backup; processing_lisr = processing_lisr_backup; if (KAL_FALSE == SLA_IsLmuLogging()) { LMU_Write_ISR_END_CSM(0xaaaaaaaa); if( processing_irqx != IRQ_NOT_LISR_CONTEXT ) { LMU_Write_ISR_RESUME_CSM(0xaaaa0000 | ((kal_uint32)processing_irqx)); } } if (SA_LoggingIndex != 0) { SLA_LoggingLISR(0xaaaaaaaa); } #if defined __MALMO_ASM_SWTR__ ST_MALMO_ASM_ChangeContextID(); #endif /* __MALMO_ASM_SWTR */ /* Binary-coded IRQ idx */ SYS_ClearInt2((kal_uint8)irqx); }
/** @argu mode : to be defined, currently no usage. * **/ kal_int32 arm_enter_standby_mode(kal_int32 mode) { #if defined (__CPU_ARM7EJ_S__) || defined (__CPU_ARM7TDMI__) //without cp15 wfi #if defined (MT6250) #if !defined (SLEEP_CON) #define ARM_SLEEP_CON ((volatile UINT16P)(ARM_CONFG_base+0x0040)) #define SLEEP_CON ARM_SLEEP_CON #endif kal_uint32 tmp; tmp = *PLL_CLK_CONDA; ASSERT(((tmp >> 10) & 0x3f) == 0x21); // assert RG_ARM_PLLCK_SEL1 as 87Mhz, and RG_ARM_PLLCK_SEL2 as 260Mhz *PLL_CLK_CONDC = (*PLL_CLK_CONDC & ~(0x7<<3)) | (0x2<<3); *PLL_CLK_CONDC; /** ASTONE, * "READ-modify-write" is good for flushing bus transaction, instead of write directly. * BUT, take care about side effect of read-modify-write, esp. about read-clear bit. **/ *SLEEP_CON |= 1; __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); /* debug code of long irq latency of TDMA issue. Should be removed after W12.26 */ { extern kal_uint32 irq_dbg_time_leave_from_sleep; irq_dbg_time_leave_from_sleep = ust_get_current_time(); } *PLL_CLK_CONDC = (*PLL_CLK_CONDC & ~(0x7<<3)) | (0x4<<3); *PLL_CLK_CONDC; #elif defined (MT6260) #if !defined (SLEEP_CON) #define ARM_SLEEP_CON ((volatile UINT16P)(ARM_CONFG_base+0x0040)) #define SLEEP_CON ARM_SLEEP_CON #endif { register kal_uint32 conda, condc, conde; kal_uint32 _savedmask; kal_uint32 LockIRQ(void); void RestoreIRQ(kal_uint32); _savedmask = LockIRQ(); conda = *PLL_CLK_CONDA; condc = *PLL_CLK_CONDC; /* if (mode != 0) { */ /* conde = *PLL_CLK_CONDE; */ /* *PLL_CLK_CONDE = conde & (3<<14); */ /* } */ // switch MCU to MPLL/3 clock; /* *PLL_CLK_CONDA = (conda | (1<<13)); */ /* *PLL_CLK_CONDC = (condc & ~(0x7<<3) | (0x04 << 3)); */ *PLL_CLK_CONDC = (condc & ~(0x7<<3) | (0x01 << 3)); *PLL_CLK_CONDC; #if defined(MT6260) && defined(__ESD_LU_NEW_SOLUTION__) #if !defined(__ESD_LU_NEW_SOLUTION_TEST__) if (*((volatile unsigned int *)(0xA0700E24))) #endif /* defined(__ESD_LU_NEW_SOLUTION_TEST__) */ { kal_uint32 t1, t2; #if !defined(__ESD_LU_NEW_SOLUTION_TEST__) if (++dropVoltageCount > 100) { // 0.8V *((volatile kal_uint16 *)(0xA0700230)) = 0x8541; *((volatile kal_uint16 *)(0xA0700230)); EXT_ASSERT(0, 0, 0, 0); } #endif /* defined(__ESD_LU_NEW_SOLUTION_TEST__) */ // 0.975V *((volatile kal_uint16 *)(0xA0700230)) = 0x85B1; *((volatile kal_uint16 *)(0xA0700230)); t1 = ust_get_current_time(); do { t2 = ust_get_current_time(); } while(ust_get_duration(t1, t2) < 500); // 1.3V *((volatile kal_uint16 *)(0xA0700230)) = 0x8481; *((volatile kal_uint16 *)(0xA0700230)); t1 = ust_get_current_time(); do { t2 = ust_get_current_time(); } while(ust_get_duration(t1, t2) < 200); } #endif /* defined(__ESD_LU_NEW_SOLUTION__) */ *SLEEP_CON |= 1; __nop(); __nop(); __nop(); __nop(); __nop(); __nop(); *PLL_CLK_CONDA = conda; *PLL_CLK_CONDC = condc; *PLL_CLK_CONDC; /* if (mode != 0) { */ /* *PLL_CLK_CONDE = conde; */ /* } */ /** disable EMI HW DCM, * 1. to workaround EMI DCM having long DCM recovery time. * 2. to workaround EMI DCM that has slow reponse MMSYS idle that make normal clock too late to reponse MMSYS request. **/ MT6260_EMI_DCM_DISABLE(); RestoreIRQ(_savedmask); } #else //#if defined (MT6250) ASSERT(0); #endif //#if defined (MT6250) #else //#if defined (__CPU_ARM7EJ_S__) || defined (__CPU_ARM7TDMI__) //without cp15 wfi cp15_enter_low_pwr_state(); #endif //#if defined (__CPU_ARM7EJ_S__) || defined (__CPU_ARM7TDMI__) //without cp15 wfi return 0; }