static int uvd_v5_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; bool enable = (state == AMD_CG_STATE_GATE) ? true : false; static int curstate = -1; if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) return 0; if (curstate == state) return 0; curstate = state; if (enable) { /* disable HW gating and enable Sw gating */ uvd_v5_0_set_sw_clock_gating(adev); } else { /* wait for STATUS to clear */ if (uvd_v5_0_wait_for_idle(handle)) return -EBUSY; /* enable HW gates because UVD is idle */ /* uvd_v5_0_set_hw_clock_gating(adev); */ } return 0; }
static int uvd_v5_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; bool enable = (state == AMD_CG_STATE_GATE) ? true : false; if (enable) { /* wait for STATUS to clear */ if (uvd_v5_0_wait_for_idle(handle)) return -EBUSY; uvd_v5_0_enable_clock_gating(adev, true); /* enable HW gates because UVD is idle */ /* uvd_v5_0_set_hw_clock_gating(adev); */ } else { uvd_v5_0_enable_clock_gating(adev, false); } uvd_v5_0_set_sw_clock_gating(adev); return 0; }