__interrupt void vButtonInterrupt1( void )
{
long lHigherPriorityTaskWoken = pdFALSE;
/* The semaphore is only created when the build is configured to create the
low power demo. */
if( xSemaphore != NULL )
{
/* This interrupt will bring the CPU out of deep sleep and software
standby modes. Give the semaphore that was used to place the Tx task
into an indefinite sleep. */
if( uxQueueMessagesWaitingFromISR( xSemaphore ) == 0 )
{
xSemaphoreGiveFromISR( xSemaphore, &lHigherPriorityTaskWoken );
}
else
{
/* The semaphore was already available, so the task is not blocked
on it and there is no point giving it. */
}
/* If giving the semaphore caused a task to leave the Blocked state,
and the task that left the Blocked state has a priority equal to or
above the priority of the task that this interrupt interrupted, then
lHigherPriorityTaskWoken will have been set to pdTRUE inside the call
to xSemaphoreGiveFromISR(), and calling portYIELD_FROM_ISR() will cause
a context switch to the unblocked task. */
portYIELD_FROM_ISR( lHigherPriorityTaskWoken );
}
}
/**
Local function to handle outgoing bulk data
@param [in] bEP
@param [in] bEPStatus
*/
static void BulkIn(unsigned char bEP, unsigned char bEPStatus)
{
int i, iLen;
long lHigherPriorityTaskWoken = pdFALSE;
( void ) bEPStatus;
if (uxQueueMessagesWaitingFromISR( xCharsForTx ) == 0) {
// no more data, disable further NAK interrupts until next USB frame
USBHwNakIntEnable(0);
return;
}
// get bytes from transmit FIFO into intermediate buffer
for (i = 0; i < MAX_PACKET_SIZE; i++) {
if( xQueueReceiveFromISR( xCharsForTx, ( &abBulkBuf[i] ), &lHigherPriorityTaskWoken ) != pdPASS )
{
break;
}
}
iLen = i;
// send over USB
if (iLen > 0) {
USBHwEPWrite(bEP, abBulkBuf, iLen);
}
portEND_SWITCHING_ISR( lHigherPriorityTaskWoken );
}
/******************************************************************************
* Function: RtlMailboxMsgWaiting
* Desc: To get the number of message blocks are storing in a given mailbox.
* Para:
* MboxID: The identifier of the target mailbox.
* IsFromISR: Is this function is called from an ISR ?
* Return: The number of message blocks are storing in this mailbox.
******************************************************************************/
u32 RtlMailboxMsgWaiting(
IN u8 MboxID,
IN u8 IsFromISR
)
{
RTL_MAILBOX *pMbox=NULL;
u32 msg_num=0;
pMbox = RtlMBoxIdToHdl(MboxID);
if (NULL == pMbox) {
MSG_MBOX_ERR("RtlMailboxMsgWaiting: Didn't find the MBox with ID=%d\n", MboxID);
return 0;
}
#ifdef PLATFORM_FREERTOS
if (IsFromISR) {
msg_num = uxQueueMessagesWaitingFromISR(pMbox->mbox_hdl);
}
else {
msg_num = uxQueueMessagesWaiting(pMbox->mbox_hdl);
}
#endif
#ifdef PLATFORM_ECOS
// TODO: call eCos API to implement this function
#endif
return msg_num;
}
xNetworkBufferDescriptor_t *pxNetworkBufferGetFromISR( size_t xRequestedSizeBytes )
{
xNetworkBufferDescriptor_t *pxReturn = NULL;
UBaseType_t uxSavedInterruptStatus;
/*_RB_ The current implementation only has a single size memory block, so
the requested size parameter is not used (yet). */
( void ) xRequestedSizeBytes;
/* If there is a semaphore available then there is a buffer available, but,
as this is called from an interrupt, only take a buffer if there are at
least ipINTERRUPT_BUFFER_GET_THRESHOLD buffers remaining. This prevents,
to a certain degree at least, a rapidly executing interrupt exhausting
buffer and in so doing preventing tasks from continuing. */
if( uxQueueMessagesWaitingFromISR( ( xQueueHandle ) xNetworkBufferSemaphore ) > ipINTERRUPT_BUFFER_GET_THRESHOLD ) {
if( xSemaphoreTakeFromISR( xNetworkBufferSemaphore, NULL ) == pdPASS ) {
/* Protect the structure as it is accessed from tasks and interrupts. */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
{
pxReturn = ( xNetworkBufferDescriptor_t * ) listGET_OWNER_OF_HEAD_ENTRY( &xFreeBuffersList );
uxListRemove( &( pxReturn->xBufferListItem ) );
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
iptraceNETWORK_BUFFER_OBTAINED_FROM_ISR( pxReturn );
}
}
if( pxReturn == NULL ) {
iptraceFAILED_TO_OBTAIN_NETWORK_BUFFER_FROM_ISR();
}
return pxReturn;
}
// Called from TX interrupt. Read from transmit message queue and
// output byte by byte to the transmit buffer
void receiveDataFromISR() {
BaseType_t xTaskWokenByReceive = pdFALSE;
char readChar;
// Temporarily disable the transmit interrupt
PLIB_INT_SourceDisable(INT_ID_0, INT_SOURCE_USART_1_TRANSMIT);
// While the queue has available messages, read bytes and transmit
while (uxQueueMessagesWaitingFromISR(sendData.transmitQ_CD) != 0){
while (xQueueReceiveFromISR(sendData.transmitQ_CD, (void *) &readChar, &xTaskWokenByReceive) )
{
// A character was received. Transmit the character now.
if (sendData.testCount % BREAK_MESSAGE_DIV != 2) // Error simulation constant (missing byte)
PLIB_USART_TransmitterByteSend(USART_ID_1, readChar);
// Duplicate data error simulation constant
if (sendData.testCount % ADD_MESSAGE_DIV == 1)
PLIB_USART_TransmitterByteSend(USART_ID_1, readChar);
// If removing the character from the queue woke the task that was
// posting onto the queue cTaskWokenByReceive will have been set to
// pdTRUE. No matter how many times this loop iterates only one
// task will be woken.
sendData.testCount++;
}
}
}
bool ISR_BufferCapacity()
{
unsigned portBASE_TYPE uxBufLen = uxQueueMessagesWaitingFromISR(s_QueueBuff);
if (uxBufLen < 128)
return false;
return true;
}
static void CAN_handle_isr(const can_t can)
{
can_struct_t *pStruct = CAN_STRUCT_PTR(can);
LPC_CAN_TypeDef *pCAN = pStruct->pCanRegs;
const uint32_t rbs = (1 << 0);
const uint32_t ibits = pCAN->ICR;
UBaseType_t count;
can_msg_t msg;
/* Handle the received message */
if ((ibits & intr_rx) | (pCAN->GSR & rbs)) {
if( (count = uxQueueMessagesWaitingFromISR(pStruct->rxQ)) > pStruct->rxQWatermark) {
pStruct->rxQWatermark = count;
}
can_msg_t *pHwMsgRegs = (can_msg_t*) &(pCAN->RFS);
if (xQueueSendFromISR(pStruct->rxQ, pHwMsgRegs, NULL)) {
pStruct->rxMsgCount++;
}
else {
pStruct->droppedRxMsgs++;
}
pCAN->CMR = 0x04; // Release the receive buffer, no need to bitmask
}
/* A transmit finished, send any queued message(s) */
if (ibits & intr_all_tx) {
if( (count = uxQueueMessagesWaitingFromISR(pStruct->txQ)) > pStruct->txQWatermark) {
pStruct->txQWatermark = count;
}
if (xQueueReceiveFromISR(pStruct->txQ, &msg, NULL)) {
CAN_tx_now(pStruct, &msg);
}
}
/* We only enable interrupt when a valid callback exists, so no need
* to check for the callback function being NULL
*/
if (ibits & g_can_bus_err_intr) {
pStruct->bus_error(ibits);
}
if (ibits & intr_ovrn) {
pStruct->data_overrun(ibits);
}
}
void TIM6_IRQHandler(void)
{
static float CurentValue_MOTOR[3];
static portBASE_TYPE xStatus;
static Moment_Typedef Moment;
static float Moments[3];
static long PWM_MOTOR[3];
static uint16_t Count = 0;
if(TIM_GetITStatus(TIM6, TIM_IT_Update) != RESET)
{
while(FIR_CollectData(SEN_MOTOR1, TSVN_ACS712_Read(ACS_1)) != DONE);
CurentValue_MOTOR[MOTOR1] = AMES_Filter(SEN_MOTOR1) - ACS1_CALIB;
while(FIR_CollectData(SEN_MOTOR2 ,TSVN_ACS712_Read(ACS_2)) != DONE);
CurentValue_MOTOR[MOTOR2] = AMES_Filter(SEN_MOTOR2) - ACS2_CALIB;
while(FIR_CollectData(SEN_MOTOR3,TSVN_ACS712_Read(ACS_3)) != DONE);
CurentValue_MOTOR[MOTOR3] = AMES_Filter(SEN_MOTOR3) - ACS3_CALIB;
if (Count++>= 300)
{
printf("%0.5f\n", CurentValue_MOTOR[MOTOR1]);
Count = 0;
}
PWM_MOTOR[MOTOR1] = PID_Calculate(MOTOR1, 550.0, CurentValue_MOTOR[MOTOR1]);
if (PWM_MOTOR[MOTOR1] < 0)
DIR_Change(MOTOR1, RESERVE);
else
DIR_Change(MOTOR1, FORWARD);
TSVN_PWM_TIM5_Set_Duty(abs(PWM_MOTOR[MOTOR1]), MOTOR1_PWM);
TIM_ClearITPendingBit(TIM6, TIM_IT_Update);
// PWM_MOTOR[MOTOR2] = PID_Calculate(MOTOR2, 300.0, CurentValue_MOTOR[MOTOR2]);
// if (PWM_MOTOR[MOTOR2] < 0)
// DIR_Change(MOTOR2, RESERVE);
// else
// DIR_Change(MOTOR2, FORWARD);
// TSVN_PWM_TIM5_Set_Duty(abs(PWM_MOTOR[MOTOR2]), MOTOR2_PWM);
//
// PWM_MOTOR[MOTOR3] = PID_Calculate(MOTOR3, 300.0, CurentValue_MOTOR[MOTOR3]);
//
// if (PWM_MOTOR[MOTOR3] < 0)
// DIR_Change(MOTOR3, RESERVE);
// else
// DIR_Change(MOTOR3, FORWARD);
// TSVN_PWM_TIM5_Set_Duty(abs(PWM_MOTOR[MOTOR3]), MOTOR3_PWM);
//
if (uxQueueMessagesWaitingFromISR(Moment_Queue) != NULL)
{
xStatus = xQueueReceiveFromISR(Moment_Queue, &Moment, 0);
if (xStatus == pdPASS)
{
Moments[0] = Moment.Mx;
Moments[1] = Moment.My;
Moments[2] = Moment.Mz;
}
}
}
}
static void USBFrameHandler(unsigned short wFrame)
{
( void ) wFrame;
if( uxQueueMessagesWaitingFromISR( xCharsForTx ) > 0 )
{
// data available, enable NAK interrupt on bulk in
USBHwNakIntEnable(INACK_BI);
}
}
static int getMaxWaiting(xQueueHandle* xQueue, int prevPeak) {
// We get here before the current item is added to the queue.
// Must add 1 to get the peak value.
unsigned portBASE_TYPE waiting = uxQueueMessagesWaitingFromISR(xQueue) + 1;
if (waiting > prevPeak) {
return waiting;
}
return prevPeak;
}
/**
* Pick up a transmission from scratch or continue an on-going transmission
* Context: ISR ONLY
* @param handle Handle to device
*/
static void pca9665_try_tx_from_isr(int handle, portBASE_TYPE * pxTaskWoken) {
uint8_t flags = 0;
if (device[handle].is_initialised == 0)
return;
if (uxQueueMessagesWaitingFromISR(device[handle].tx.queue) > 0 || device[handle].tx.frame != NULL) {
device[handle].is_busy = 1;
flags |= CON_STA;
} else {
device[handle].is_busy = 0;
flags |= CON_STO;
}
/* Send the start/stop/restart condition */
device[handle].mode = DEVICE_MODE_M_T;
pca9665_write_reg(handle, I2CCON, CON_ENSIO | CON_MODE | CON_AA | flags);
}
int csp_queue_size_isr(csp_queue_handle_t handle) {
return uxQueueMessagesWaitingFromISR(handle);
}
void UartDev::handleInterrupt()
{
/**
* Bit Masks of IIR register Bits 3:1 that contain interrupt reason.
* Bits are shifted left because reasonForInterrupt contains Bits 3:0
*/
const uint16_t transmitterEmpty = (1 << 1);
const uint16_t dataAvailable = (2 << 1);
const uint16_t dataTimeout = (6 << 1);
long higherPriorityTaskWoken = 0;
long switchRequired = 0;
char c = 0;
unsigned charsSent = 0;
uint16_t reasonForInterrupt = (mpUARTRegBase->IIR & 0xE);
{
/**
* If multiple sources of interrupt arise, let this interrupt exit, and re-enter
* for the new source of interrupt.
*/
switch (reasonForInterrupt)
{
case transmitterEmpty:
{
if(uxQueueMessagesWaitingFromISR(mTxQueue) > mTxQWatermark) {
mTxQWatermark = uxQueueMessagesWaitingFromISR(mTxQueue);
}
/**
* When THRE (Transmit Holding Register Empty) interrupt occurs,
* we can send as many bytes as the hardware FIFO supports (16)
*/
const unsigned char hwTxFifoSize = 16;
for(charsSent=0;
charsSent < hwTxFifoSize && xQueueReceiveFromISR(mTxQueue, &c, &higherPriorityTaskWoken);
charsSent++)
{
mpUARTRegBase->THR = c;
if(higherPriorityTaskWoken) {
switchRequired = 1;
}
}
}
break;
case dataAvailable:
case dataTimeout:
{
mLastActivityTime = xTaskGetTickCountFromISR();
/**
* While receive Hardware FIFO not empty, keep queuing the data.
* Even if xQueueSendFromISR() Fails (Queue is full), we still need to
* read RBR register otherwise interrupt will not clear
*/
while (0 != (mpUARTRegBase->LSR & (1 << 0)))
{
c = mpUARTRegBase->RBR;
xQueueSendFromISR(mRxQueue, &c, &higherPriorityTaskWoken);
if(higherPriorityTaskWoken) {
switchRequired = 1;
}
}
if(uxQueueMessagesWaitingFromISR(mRxQueue) > mRxQWatermark) {
mRxQWatermark = uxQueueMessagesWaitingFromISR(mRxQueue);
}
}
break;
default:
/* Read LSR register to clear Line Status Interrupt */
reasonForInterrupt = mpUARTRegBase->LSR;
break;
}
}
portEND_SWITCHING_ISR(switchRequired);
}
