static char cGetAck( char cBus )
{
// SDA = wireLOW;
vSetSDA( cBus, wireLOW );
// SCL = wireLOW;
vSetSCL( cBus, wireLOW );
/* Ensure clock is low */
// SCL_TRIS = wireLOW;
vSetSCL_TRIS( cBus, wireLOW );
/* Release the data pin so slave can ACK */
// SDA_TRIS = wireHIGH;
vSetSDA_TRIS( cBus, wireHIGH );
/* Release the clock pin */
// SCL_TRIS = wireHIGH;
vSetSCL_TRIS( cBus, wireHIGH );
vDelay( wireHALFCLOCK );
// if( SDA )
if( cGetSDA( cBus ) != wireLOW )
{
/* No ACK */
return 0;
}
vDelay( wireHALFCLOCK );
/* Finish the clock pulse */
// SCL_TRIS = wireLOW;
vSetSCL_TRIS( cBus, wireLOW );
vDelay( wireCLOCKLOW );
vDelay( wireCLOCKLOW );
return 1;
}
static void vClock( char cBus )
{
vDelay(wireDATASETTLE);
// SCL_TRIS = wireHIGH;
vSetSCL_TRIS( cBus, wireHIGH );
vDelay(wireCLOCKHIGH);
// SCL_TRIS = wireLOW;
vSetSCL_TRIS( cBus, wireLOW );
vDelay(wireCLOCKLOW);
}
static void vSendNack( char cBus )
{
// SDA = 0;
vSetSDA( cBus, wireLOW );
// SDA_TRIS = wireLOW;
vSetSDA_TRIS( cBus, wireHIGH );
vDelay( wireDATASETTLE );
vClock( cBus );
// SDA_TRIS = wireHIGH;
vDelay( wireDATASETTLE );
}
UINT32 brdCheckCpciIsSyscon (void *ptr)
{
UINT8 bFlag = 0;
UINT8 bTemp1 = 0, bTemp2 = 0;
#ifdef DEBUG_SOAK
char buffer[32];
#endif
(void)ptr;
bTemp1 = dIoReadReg(CPCI_STATUS, REG_8);
#ifdef DEBUG_SOAK
sprintf(buffer,"1. CPCI_STATUS bTemp1:%#x \n",bTemp1);
sysDebugWriteString(buffer);
vDelay(10);
#endif
bTemp1 = (bTemp1) & (FORCE_SAT|CPCI_PRESENT);
#ifdef DEBUG_SOAK
vDelay(10);
sprintf(buffer,"2. bTemp1:%#x \n",bTemp1);
sysDebugWriteString(buffer);
vDelay(10);
#endif
bTemp2 = dIoReadReg(CPCI_STATUS, REG_8);
bTemp2 = (bTemp2) & (CPCI_SYSEN);
#ifdef DEBUG_SOAK
vDelay(1000);
sprintf(buffer,"3. bTemp2:%#x \n",bTemp2);
sysDebugWriteString(buffer);
vDelay(10);
#endif
if ( (bTemp1 == CPCI_PRESENT) && (bTemp2 != CPCI_SYSEN) )
{
bFlag = 1;
}
else
{
bFlag = 0;
}
*((UINT8*)ptr) = bFlag;
return (E__OK);
}
static char cGetByte( char cBus )
{
char cCount,
cByte = 0;
// SDA = wireLOW;
vSetSDA( cBus, wireLOW );
// SCL = wireLOW;
vSetSCL( cBus, wireLOW );
vDelay( wireCLOCKLOW );
for( cCount = 8; cCount; --cCount )
{
cByte = cByte << 1;
/* Release the pin */
// SDA_TRIS = wireHIGH;
vSetSDA_TRIS( cBus, wireHIGH );
cByte |= cReadBit( cBus );
}
return cByte;
}
static void vStop( char cBus )
{
/* I2C Stop condition */
// SDA_TRIS = wireLOW;
vSetSDA_TRIS( cBus, wireLOW );
// SCL_TRIS = wireHIGH;
vSetSCL_TRIS( cBus, wireHIGH );
vDelay(wireSTOPDELAY);
// SDA_TRIS = wireHIGH;
vSetSDA_TRIS( cBus, wireHIGH );
}
static UINT32 wLoopbackTest (void)
{
UINT8 bTmp;
char achErrTxt [80];
//Configure GPIO7 as output and all others as input and test loopback
vIoWriteReg (GPIO_DIR_REG,REG_8,0x80);
vDelay(2);
bTmp = dIoReadReg (GPIO_STATUS_REG,REG_8);
bTmp |= GPIO7_DIR_DATA;
/*Write 1 to GPIO7 register*/
vIoWriteReg(GPIO_STATUS_REG, REG_8,bTmp);
vDelay(2);
bTmp = dIoReadReg (GPIO_STATUS_REG,REG_8);
vDelay(2);
if(bTmp != 0xff)
{
sprintf (achErrTxt, "Expected bits '1' received '0' on all GPIOs\n");
vConsoleWrite (achErrTxt);
return E__ERR_1;
}
//Write 0 to GPIO 7 and check on other ports
bTmp&= ~(GPIO7_DIR_DATA);
vIoWriteReg(GPIO_STATUS_REG, REG_8,bTmp);
vDelay(5);
bTmp = dIoReadReg (GPIO_STATUS_REG,REG_8);
if(bTmp != 0x00)
{
sprintf (achErrTxt, "Expected bits '0' received '1' on all GPIO\n");
vConsoleWrite (achErrTxt);
return E__ERR_2;
}
return E__OK;
}
static char cReadBit( char cBus )
{
char cBit = 0;
vDelay( wireDATASETTLE );
// SCL_TRIS = wireHIGH;
vSetSCL_TRIS( cBus, wireHIGH );
vDelay( wireHALFCLOCK );
// if( SDA != 0 )
if ( cGetSDA( cBus ) != wireLOW )
{
cBit = 1;
}
vDelay(wireHALFCLOCK);
// SCL_TRIS = wireLOW;
vSetSCL_TRIS( cBus, wireLOW );
vDelay(wireCLOCKLOW);
return cBit;
}
static void vStart( char cBus )
{
/* Ensure pins are in high-Z mode */
// SDA_TRIS = wireHIGH;
vSetSDA_TRIS( cBus, wireHIGH );
// SCL_TRIS = wireHIGH;
vSetSCL_TRIS( cBus, wireHIGH );
// SCL = wireLOW;
vSetSCL( cBus, wireLOW );
// SDA = wireLOW;
vSetSDA( cBus, wireLOW );
vDelay( wireSTARTDELAY );
/* I2C Start condition */
// SDA_TRIS = wireLOW;
vSetSDA_TRIS( cBus, wireLOW );
// SDA = wireLOW;
vSetSDA( cBus, wireLOW );
vDelay( wireSTARTDELAY );
// SCL_TRIS = wireLOW;
vSetSCL_TRIS( cBus, wireLOW );
vDelay( wireCLOCKLOW );
}
// **********************FONCTION: vI2C_WaitInterrupt()*************************
//
// DESCRIPTION: Permet d'attendre qu'un interrupt survient
//
// INCLUDE: "_DeclarationGenerale.h"
// "CLI2CHard.h"
//
// PROTOTYPE: void vI2C_WaitInterrupt(void)
//
// PROCEDURE D'APPEL: vI2C_WaitInterrupt()
//
// PARAMETRE D'ENTREE: AUCUN
//
// PARAMETRE DE SORTIE: AUCUN
//
// EXEMPLE: vI2C_WaitInterrupt() ---> Attend un interrupt
//
// Auteur: Vincent Chouinard
// Date: 16 septembre 2014 (Version 1.0)
// Modification:
// *****************************************************************************
void CLI2CHARD :: vI2C_WaitInterrupt(void)
{
i2cwait = 1; // Flag d'attente
i2c_timeout = 0; // Flag de depassement d'attente
while (i2cwait == 1) // Wait for int to clear flag
{ //
if(i2c_timeout >= 2 ) // XmS timeout loop
{ //
i2c_timeout_flag = 1; // set error flag
i2cwait = 0; // Reset le flag d'attente
} //
vDelay(i); // 1 mS delay (approximatively)
i2c_timeout++; // for the timeloop
}
}
static char cSendByte( char cBus, char cByte )
{
char cCount;
// SDA = wireLOW;
vSetSDA( cBus, wireLOW );
// SCL = wireLOW;
vSetSCL( cBus, wireLOW );
/* Give clock time to go low */
vDelay( wireCLOCKLOW );
/* Send 8 bits */
for( cCount = 8; cCount; --cCount )
{
/* Get next bit from byte */
if( (cByte & 0x80) == 0 )
{
/* Pull pin low */
// SDA = wireLOW;
vSetSDA( cBus, wireLOW );
// SDA_TRIS = wireLOW;
vSetSDA_TRIS( cBus, wireLOW );
}
else
{
/* Release pin */
// SDA_TRIS = wireHIGH;
vSetSDA_TRIS( cBus, wireHIGH );
}
cByte = cByte << 1;
vClock( cBus );
}
// SDA_TRIS = wireHIGH;
vSetSDA_TRIS( cBus, wireHIGH );
return wireSTATUS_SUCCESS;
}
static int
idtg2_route_add_entry(struct rio_mport *mport, UINT16 destid, UINT8 hopcount,
UINT16 table, UINT16 route_destid, UINT8 route_port)
{
/*
* Select routing table to update
*/
#ifdef DEBUG_SRIO
sysDebugWriteString("\nIn:idtg2_route_add_entry\n");
#endif
if (table == RIO_GLOBAL_TABLE)
table = 0;
else
table++;
if (route_port == RIO_INVALID_ROUTE)
route_port = IDT_DEFAULT_ROUTE;
rio_mport_write_config_32(mport, destid, hopcount,
LOCAL_RTE_CONF_DESTID_SEL, table);
/*
* Program destination port for the specified destID
*/
rio_mport_write_config_32(mport, destid, hopcount,
RIO_STD_RTE_CONF_DESTID_SEL_CSR,
(UINT32)route_destid);
rio_mport_write_config_32(mport, destid, hopcount,
RIO_STD_RTE_CONF_PORT_SEL_CSR,
(UINT32)route_port);
vDelay(10);
#ifdef DEBUG_SRIO
sysDebugWriteString("\nOut:idtg2_route_add_entry\n");
#endif
return 0;
}
/*****************************************************************************
* c_entry: this is our main() function, called from boot_prot.S
*
* RETURNS: None
*/
__attribute__((regparm(0))) void c_entry (void)
{
xTaskHandle xHandle;
UINT8 i=0,bFlag = 0;
UINT16 port, baud = 0;
NV_RW_Data nvdata;
#ifdef INCLUDE_DEBUG_VGA
char achBuffer[80];
#endif
#if 0 /* Not used, HAL no longer present */
/*
* Register the local service provider now, as code will be using BIT
* services for PCI accesses.
*/
cctRegisterServiceProvider (cctServiceProvider);
#endif
/*
* Key sub-system initialisation
*/
sysMmuInitialize (); /* Initialise the local page table management */
sysInitMalloc (K_HEAP, U_HEAP); /* Initialise the heap management */
#ifdef INCLUDE_EXCEPTION_DEBUG
dbgInstallExceptionHandlers();
#endif
#ifdef INCLUDE_DBGLOG
dbgLogInit();
#endif
/*Initialise the mutexes so that we can start using the public functions*/
for(i=0; i < MAX_CUTEBIT_MUTEX; i++)
{
globalMutexPool[i]=xSemaphoreCreateMutex();
if( globalMutexPool[i] == NULL )
{
/*We should not get here, die...*/
while(1);
}
}
/*
* Search and parse BIOS_INFO and EXTENDED_INFO structures
*/
board_service(SERVICE__BRD_GET_BIOS_INFO, NULL, &dBiosInfo_addr);
board_service(SERVICE__BRD_GET_EXTENDED_INFO, NULL, NULL);
/*
* Open/close the debug channel and sign-on - we can't use vDebugWrite() this
* early, so make direct calls to sysDebug...
*/
if(bStartupDebugMode())
{
sysDebugWriteString ("\n[Debugging Enabled]\n");
if(sysIsDebugopen())
{
if(board_service(SERVICE__BRD_GET_FORCE_DEBUG_OFF, NULL, NULL) == E__OK)
{
sysDebugWriteString ("[Debugging Forced Off]\n");
sysDebugClose();
}
}
}
else if( board_service(SERVICE__BRD_GET_FORCE_DEBUG_ON, NULL, NULL) == E__OK )
{
sysDebugWriteString ("[Debugging Forced On]\n");
bForceStartupDebugMode();
sysDebugOpen();
}
sysDebugFlush ();
#ifdef INCLUDE_DEBUG_VGA
vgaDisplayInit();
vgaSetCursor( CURSOR_OFF );
#endif
sysDebugWriteString ("Starting HW Initialization\n");
board_service(SERVICE__BRD_HARDWARE_INIT, NULL, NULL); /* board-specific H/W initialisation */
if(board_service(SERVICE__BRD_GET_CONSOLE_PORT, NULL, &port) == E__OK)
{
baud = bGetBaudRate();
//baud = 0; //hard coded by Rajan. Need to remove after debug
sysSccInit (port, baud);
#ifdef INCLUDE_DEBUG_VGA
sprintf( achBuffer, "Console open, port: 0x%x baud: %u\n", port, baud );
vgaPutsXY( 0, startLine++, achBuffer );
#endif
}
if(board_service(SERVICE__BRD_GET_DEBUG_PORT, NULL, &port) == E__OK)
{
//#ifdef commented by Rajan. Need to uncomment after debug
//#ifdef INCLUDE_DEBUG_PORT_INIT
baud = bGetBaudRate();
baud = 0; //hard coded by Rajan. Need to remove after debug
sysSccInit (port, baud);
//#endif
#ifdef INCLUDE_DEBUG_VGA
sprintf( achBuffer, "Debug %s, port: 0x%x baud: %u\n",
(sysIsDebugopen()? "open":"closed"), port, baud );
vgaPutsXY( 0, startLine++, achBuffer );
#endif
}
#ifdef INCLUDE_MAIN_DEBUG
{
UINT32 temp = 0;
board_service(SERVICE__BRD_GET_MAX_DRAM_BELOW_4GB, NULL, &temp);
DBLOG( "Max DRAM below 4GB: 0x%08x\n", temp );
}
#endif
#if defined(MAKE_CUTE) || defined (MAKE_BIT_CUTE)
#if defined(VPX)
vpxPreInit();
#endif
#if defined(CPCI)
board_service(SERVICE__BRD_CHECK_CPCI_IS_SYSCON,NULL,&bFlag);
cpciPreInit(bFlag);
#endif
board_service(SERVICE__BRD_CONFIGURE_VXS_NT_PORTS, NULL, NULL);
#endif
#if defined (SRIO)
sysDebugWriteString ("Initializing: SRIO\n");
for (i = 1 ; i < MAX_TSI721_DEVS; i++)
{
srioPreInit (i);
}
#endif
#ifndef CPCI
if (!bFlag)
vDelay(2000);// delay added, so pmc160 will show up!
#endif
sysDebugWriteString ("Initializing: PCI\n");
sysPciInitialize (); /* (re)scan PCI and allocate resources */
sysDebugWriteString ("Rajan--> Step1\n");
#if defined(MAKE_CUTE) || defined (MAKE_BIT_CUTE)
#if defined (VME) && defined (INCLUDE_LWIP_SMC)
// pci bus enumeration must have been run
InitialiseVMEDevice();
#endif
#endif
sysDebugWriteString ("Rajan--> Step2\n");
#ifdef INCLUDE_DEBUG_VGA
vgaPutsXY( 0, startLine, "FreeRTOS starting....\n\n" );
startLine += 2;
#endif
board_service(SERVICE__BRD_POST_SCAN_INIT, NULL, NULL); // post scan H/W initialisations
board_service(SERVICE__BRD_ENABLE_SMIC_LPC_IOWINDOW, NULL, NULL); /* board-specific smic Initialization */
/*
* Having got this far, clear the load error that we've been holding in CMOS
*/
nvdata.dNvToken = NV__TEST_NUMBER;
nvdata.dData = 0;
board_service(SERVICE__BRD_NV_WRITE, NULL, &nvdata);
nvdata.dNvToken = NV__ERROR_CODE;
nvdata.dData = E__BOARD_HANG;
board_service(SERVICE__BRD_NV_WRITE, NULL, &nvdata);
#ifdef INCLUDE_MAIN_DEBUG
DBLOG( "CUTE/BIT Kernel heap: 0x%08x-0x%08x\n", (UINT32)K_HEAP, ((UINT32)K_HEAP + HEAP_SIZE - 1) );
DBLOG( "CUTE/BIT User heap : 0x%08x-0x%08x\n", (UINT32)U_HEAP, ((UINT32)U_HEAP + HEAP_SIZE - 1) );
xPortGetFreeHeapSize();
#endif
/* Initialise task data */
vTaskDataInit( bCpuCount );
/* Initialise PCI shared interrupt handling */
pciIntInit();
#ifdef INCLUDE_MAIN_DEBUG
pciListDevs( 0 );
#endif
/* Create and start the network */
sysDebugWriteString ("Initializing: Network\n");
networkInit();
#if defined(SRIO)
sysDebugWriteString ("Initializing: TSI721\n");
for (i = 1 ; i < MAX_TSI721_DEVS; i++)
{
tsi721_init(i);
}
rio_init_mports();
#endif
// some boards may not reset the RTC cleanly
board_service(SERVICE__BRD_INIT_RTC, NULL, NULL);
#ifdef INCLUDE_DEMO_TASKS
randMutex = xSemaphoreCreateMutex();
if (randMutex == NULL)
{
sysDebugWriteString ("Error - Failed to create rand mutex\n");
}
else
{
for (i = 0; i < bCpuConfigured; i++)
{
tParam[i].taskNum = i + 1;
sprintf( tParam[i].taskName, "Demo%u", tParam[i].taskNum );
xTaskCreate( i, vTaskCodePeriodic, tParam[i].taskName, mainDEMO_STACK_SIZE,
&tParam[i], mainDEMO_TASK_PRIORITY, &xHandle );
}
tParam[i].taskNum = i + 1;
sprintf( tParam[i].taskName, "BKGRD" );
xTaskCreate( 0, vTaskCodeBackground, tParam[i].taskName, mainDEMO_STACK_SIZE,
&tParam[i], mainDEMO_TASK_PRIORITY+1, &xHandle );
}
#endif
sysDebugWriteString ("Creating CUTE task\n");
xTaskCreate( 0, startCuteBit, "CuteBitTask", mainCUTEBIT_TASK_STACKSIZE,
NULL, mainCUTEBIT_TASK_PRIORITY, &xHandle );
#ifdef INCLUDE_MAIN_DEBUG
sysDebugWriteString ("\n[Starting FreeRtos Scheduler]\n");
sysDebugFlush ();
#endif
sysInvalidateTLB();
/* Start the FreeRTOS Scheduler, does not return */
vTaskStartScheduler();
} /* c_entry () */
/****************************************************************************************
* Configure the EMI for the SDRAM
*
* - on the Hitex board (IS42S16400D-7TL)
* - on the NXP validation board (MT48LC4M32B2)
*
****************************************************************************************/
void EMC_Init_SRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
{
// calculate a 1 usec delay base
delayBase1us = M4Frequency / DELAY_1usFreq;
// eventually adjust the CCU delays for EMI (default to zero)
initEmiDelays();
// Initialize EMC to interface with SDRAM. The EMC needs to run for this.
LPC_EMC->CONTROL = 0x00000001; // (Re-)enable the external memory controller
LPC_EMC->CONFIG = 0;
#if (PLATFORM == HITEX_A2_BOARD)
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14)); // Selects the configuration information for dynamic memory chip select 0.
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8); // Selects the RAS and CAS latencies for dynamic memory chip select 0.
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY; // Configures the dynamic memory read strategy.
LPC_EMC->DYNAMICRP = 1; // Selects the precharge command period
LPC_EMC->DYNAMICRAS = 3; // Selects the active to precharge command period
LPC_EMC->DYNAMICSREX = 5; // Selects the self-refresh exit time
LPC_EMC->DYNAMICAPR = 0; // Selects the last-data-out to active command time
LPC_EMC->DYNAMICDAL = 4; // Selects the data-in to active command time.
LPC_EMC->DYNAMICWR = 1; // Selects the write recovery time
LPC_EMC->DYNAMICRC = 5; // Selects the active to active command period
LPC_EMC->DYNAMICRFC = 5; // Selects the auto-refresh period
LPC_EMC->DYNAMICXSR = 5; // Selects the exit self-refresh to active command time
LPC_EMC->DYNAMICRRD = 0; // Selects the active bank A to active bank B latency
LPC_EMC->DYNAMICMRD = 0; // Selects the load mode register to active command time
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
vDelay(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2; // Configures dynamic memory refresh operation
vDelay(100);
LPC_EMC->DYNAMICREFRESH = 83; // Configures dynamic memory refresh operation
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// Write configuration data to SDRAM device
if(u32DataBus == 0) { // 16-bit data bus, the EMC enforces a burst size 8
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
} else { // burst size 4 (which is not an option for 16-bit data bus anyway)
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
#endif // HITEX_BOARD
#if (PLATFORM == NXP_VALIDATION_BOARD)
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (u32DataBus << 14));
LPC_EMC->DYNAMICRASCAS0 = (2UL << 0) | (2UL << 8);
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
LPC_EMC->DYNAMICRAS = 2;
LPC_EMC->DYNAMICSREX = 5;
LPC_EMC->DYNAMICAPR = 0;
LPC_EMC->DYNAMICDAL = 4;
LPC_EMC->DYNAMICWR = 1;
LPC_EMC->DYNAMICRC = 5;
LPC_EMC->DYNAMICRFC = 5;
LPC_EMC->DYNAMICXSR = 5;
LPC_EMC->DYNAMICRRD = 0;
LPC_EMC->DYNAMICMRD = 0;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
vDelay(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2;
vDelay(100);
LPC_EMC->DYNAMICREFRESH = 83;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
// Write configuration data to SDRAM device
if(u32DataBus == 0) { // burst size 8
*((volatile uint32_t *)(u32BaseAddr | ((3UL | (2UL << 4)) << (u32ColAddrBits + 2 + 1))));
} else { // burst size 4
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2 + 2))));
}
#endif // Validation board
LPC_EMC->DYNAMICCONTROL = 0;
LPC_EMC->DYNAMICCONFIG0 |= EMC_B_ENABLE; // Enable the buffers
}
