static int init_rk3066b_lcdc(struct rk_lcdc_device_driver *dev_drv) { int i=0; int __iomem *c; int v; struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); if(lcdc_dev->id == 0) //lcdc0 { lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); } else if(lcdc_dev->id == 1) { lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); } else { printk(KERN_ERR "invalid lcdc device!\n"); return -EINVAL; } if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); } rk3066b_lcdc_clk_enable(lcdc_dev); if(lcdc_dev->id == 0) { #if defined(CONFIG_RK3066B_LCDC0_IO_18V) v = 0x40004000; //bit14: 1,1.8v;0,3.3v writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); #else v = 0x40000000; writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); #endif } if(lcdc_dev->id == 1) //iomux for lcdc1 { #if defined(CONFIG_RK3066B_LCDC1_IO_18V) v = 0x80008000; //bit14: 1,1.8v;0,3.3v writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); #else v = 0x80000000; writel_relaxed(v,RK30_GRF_BASE + GRF_IO_CON4); #endif iomux_set(LCDC1_DCLK); iomux_set(LCDC1_DEN); iomux_set(LCDC1_HSYNC); iomux_set(LCDC1_VSYNC); iomux_set(LCDC1_D0); iomux_set(LCDC1_D1); iomux_set(LCDC1_D2); iomux_set(LCDC1_D3); iomux_set(LCDC1_D4); iomux_set(LCDC1_D5); iomux_set(LCDC1_D6); iomux_set(LCDC1_D7); iomux_set(LCDC1_D8); iomux_set(LCDC1_D9); iomux_set(LCDC1_D10); iomux_set(LCDC1_D11); iomux_set(LCDC1_D12); iomux_set(LCDC1_D13); iomux_set(LCDC1_D14); iomux_set(LCDC1_D15); iomux_set(LCDC1_D16); iomux_set(LCDC1_D17); iomux_set(LCDC1_D18); iomux_set(LCDC1_D19); iomux_set(LCDC1_D20); iomux_set(LCDC1_D21); iomux_set(LCDC1_D22); iomux_set(LCDC1_D23); } LcdMskReg(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE | m_W0_AXI_OUTSTANDING2 | m_W1_AXI_OUTSTANDING2,v_LCDC_AXICLK_AUTO_ENABLE(1) | v_W0_AXI_OUTSTANDING2(1) | v_W1_AXI_OUTSTANDING2(1));//eanble axi-clk auto gating for low power LcdWrReg(lcdc_dev,AXI_MS_ID,v_HWC_CHANNEL_ID(5) | v_WIN2_CHANNEL_ID(4) | v_WIN1_YRGB_CHANNEL_ID(3) | v_WIN0_CBR_CHANNEL_ID(2) | v_WIN0_YRGB_CHANNEL_ID(1)); LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | v_SCANNING_MASK(1)); //mask all interrupt in init LcdMskReg(lcdc_dev,FIFO_WATER_MARK,m_WIN1_FIFO_FULL_LEVEL,v_WIN1_FIFO_FULL_LEVEL(0x1e0)); //LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective if(dev_drv->cur_screen->dsp_lut) //resume dsp lut { LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(0)); LCDC_REG_CFG_DONE(); mdelay(25); //wait for dsp lut disabled for(i=0;i<256;i++) { v = dev_drv->cur_screen->dsp_lut[i]; c = lcdc_dev->dsp_lut_addr_base+i; writel_relaxed(v,c); } LcdMskReg(lcdc_dev,SYS_CFG,m_DSIP_LUT_CTL,v_DSIP_LUT_CTL(1));//enable dsp lut } rk3066b_lcdc_clk_disable(lcdc_dev); return 0; }
static int rk30_lcdc_init(struct rk_lcdc_device_driver *dev_drv) { int i = 0; int __iomem *c; int v; struct rk30_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk30_lcdc_device,driver); if(lcdc_dev->id == 0) //lcdc0 { lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); } else if(lcdc_dev->id == 1) { lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); } else { printk(KERN_ERR "invalid lcdc device!\n"); return -EINVAL; } if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); } rk30_lcdc_clk_enable(lcdc_dev); rk30_lcdc_read_reg_defalut_cfg(lcdc_dev); lcdc_msk_reg(lcdc_dev,SYS_CTRL0,m_HWC_CHANNEL_ID | m_WIN2_CHANNEL_ID | m_WIN1_CBR_CHANNEL_ID | m_WIN1_YRGB_CHANNEL_ID | m_WIN0_CBR_CHANNEL1_ID | m_WIN0_YRGB_CHANNEL1_ID | m_WIN0_CBR_CHANNEL0_ID | m_WIN0_YRGB_CHANNEL0_ID,v_HWC_CHANNEL_ID(7) | v_WIN2_CHANNEL_ID(6) | v_WIN1_CBR_CHANNEL_ID(5) | v_WIN1_YRGB_CHANNEL_ID(4) | v_WIN0_CBR_CHANNEL1_ID(3) | v_WIN0_YRGB_CHANNEL1_ID(2) | v_WIN0_CBR_CHANNEL0_ID(1) | v_WIN0_YRGB_CHANNEL0_ID(0)); //channel id ,just use default value lcdc_writel(lcdc_dev,WIN0_SCL_FACTOR_YRGB,0x10001000); lcdc_writel(lcdc_dev,WIN1_SCL_FACTOR_YRGB,0x10001000); lcdc_set_bit(lcdc_dev,DSP_CTRL0, m_LCDC_AXICLK_AUTO_ENABLE);//eanble axi-clk auto gating for low power lcdc_msk_reg(lcdc_dev,INT_STATUS,m_FRM_START_INT_CLEAR | m_BUS_ERR_INT_CLEAR | m_LINE_FLAG_INT_EN | m_FRM_START_INT_EN | m_HOR_START_INT_EN,v_FRM_START_INT_CLEAR(1) | v_BUS_ERR_INT_CLEAR(0) | v_LINE_FLAG_INT_EN(0) | v_FRM_START_INT_EN(0) | v_HOR_START_INT_EN(0)); //enable frame start interrupt for sync if(dev_drv->cur_screen->dsp_lut) { lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(0)); lcdc_cfg_done(lcdc_dev); msleep(25); for(i=0;i<256;i++) { v = dev_drv->cur_screen->dsp_lut[i]; c = lcdc_dev->dsp_lut_addr_base+i; writel_relaxed(v,c); } lcdc_msk_reg(lcdc_dev,SYS_CTRL1,m_DSP_LUT_RAM_EN,v_DSP_LUT_RAM_EN(1)); } lcdc_cfg_done(lcdc_dev); // write any value to REG_CFG_DONE let config become effective rk30_lcdc_clk_disable(lcdc_dev); return 0; }
static int init_rk3066b_lcdc(struct rk_lcdc_device_driver *dev_drv) { struct rk3066b_lcdc_device *lcdc_dev = container_of(dev_drv,struct rk3066b_lcdc_device,driver); if(lcdc_dev->id == 0) //lcdc0 { lcdc_dev->pd = clk_get(NULL,"pd_lcdc0"); lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc0"); lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc0"); lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc0"); } else if(lcdc_dev->id == 1) { lcdc_dev->pd = clk_get(NULL,"pd_lcdc1"); lcdc_dev->hclk = clk_get(NULL,"hclk_lcdc1"); lcdc_dev->aclk = clk_get(NULL,"aclk_lcdc1"); lcdc_dev->dclk = clk_get(NULL,"dclk_lcdc1"); } else { printk(KERN_ERR "invalid lcdc device!\n"); return -EINVAL; } if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||(IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) { printk(KERN_ERR "failed to get lcdc%d clk source\n",lcdc_dev->id); } clk_enable(lcdc_dev->pd); clk_enable(lcdc_dev->hclk); //enable aclk and hclk for register config clk_enable(lcdc_dev->aclk); lcdc_dev->clk_on = 1; if(lcdc_dev->id == 1) //iomux for lcdc1 { rk30_mux_api_set(GPIO2D0_LCDC1DCLK_SMCCSN0_NAME,GPIO2D_LCDC1DCLK); rk30_mux_api_set(GPIO2D1_LCDC1DEN_SMCWEN_NAME,GPIO2D_LCDC1DEN); rk30_mux_api_set(GPIO2D2_LCDC1HSYNC_SMCOEN_NAME,GPIO2D_LCDC1HSYNC); rk30_mux_api_set(GPIO2D3_LCDC1VSYNC_SMCADVN_NAME,GPIO2D_LCDC1VSYNC); rk30_mux_api_set(GPIO2A0_LCDC1DATA0_SMCDATA0_TRACEDATA0_NAME,GPIO2A_LCDC1DATA0); rk30_mux_api_set(GPIO2A1_LCDC1DATA1_SMCDATA1_TRACEDATA1_NAME,GPIO2A_LCDC1DATA1); rk30_mux_api_set(GPIO2A2_LCDC1DATA2_SMCDATA2_TRACEDATA2_NAME,GPIO2A_LCDC1DATA2); rk30_mux_api_set(GPIO2A3_LCDC1DATA3_SMCDATA3_TRACEDATA3_NAME,GPIO2A_LCDC1DATA3); rk30_mux_api_set(GPIO2A4_LCDC1DATA4_SMCDATA4_TRACEDATA4_NAME,GPIO2A_LCDC1DATA4); rk30_mux_api_set(GPIO2A5_LCDC1DATA5_SMCDATA5_TRACEDATA5_NAME,GPIO2A_LCDC1DATA5); rk30_mux_api_set(GPIO2A6_LCDC1DATA6_SMCDATA6_TRACEDATA6_NAME,GPIO2A_LCDC1DATA6); rk30_mux_api_set(GPIO2A7_LCDC1DATA7_SMCDATA7_TRACEDATA7_NAME,GPIO2A_LCDC1DATA7); rk30_mux_api_set(GPIO2B0_LCDC1DATA8_SMCDATA8_TRACEDATA8_NAME,GPIO2B_LCDC1DATA8); rk30_mux_api_set(GPIO2B1_LCDC1DATA9_SMCDATA9_TRACEDATA9_NAME,GPIO2B_LCDC1DATA9); rk30_mux_api_set(GPIO2B2_LCDC1DATA10_SMCDATA10_TRACEDATA10_NAME,GPIO2B_LCDC1DATA10); rk30_mux_api_set(GPIO2B3_LCDC1DATA11_SMCDATA11_TRACEDATA11_NAME,GPIO2B_LCDC1DATA11); rk30_mux_api_set(GPIO2B4_LCDC1DATA12_SMCDATA12_TRACEDATA12_NAME,GPIO2B_LCDC1DATA12); rk30_mux_api_set(GPIO2B5_LCDC1DATA13_SMCDATA13_TRACEDATA13_NAME,GPIO2B_LCDC1DATA13); rk30_mux_api_set(GPIO2B6_LCDC1DATA14_SMCDATA14_TRACEDATA14_NAME,GPIO2B_LCDC1DATA14); rk30_mux_api_set(GPIO2B7_LCDC1DATA15_SMCDATA15_TRACEDATA15_NAME,GPIO2B_LCDC1DATA15); rk30_mux_api_set(GPIO2C0_LCDC1DATA16_SMCADDR0_TRACECLK_NAME,GPIO2C_LCDC1DATA16); rk30_mux_api_set(GPIO2C1_LCDC1DATA17_SMCADDR1_TRACECTL_NAME,GPIO2C_LCDC1DATA17); rk30_mux_api_set(GPIO2C2_LCDC1DATA18_SMCADDR2_NAME,GPIO2C_LCDC1DATA18); rk30_mux_api_set(GPIO2C3_LCDC1DATA19_SMCADDR3_NAME,GPIO2C_LCDC1DATA19); rk30_mux_api_set(GPIO2C4_LCDC1DATA20_SMCADDR4_NAME,GPIO2C_LCDC1DATA20); rk30_mux_api_set(GPIO2C5_LCDC1DATA21_SMCADDR5_NAME,GPIO2C_LCDC1DATA21); rk30_mux_api_set(GPIO2C6_LCDC1DATA22_SMCADDR6_NAME,GPIO2C_LCDC1DATA22); rk30_mux_api_set(GPIO2C7_LCDC1DATA23_SMCADDR7_NAME,GPIO2C_LCDC1DATA23); } LcdMskReg(lcdc_dev,SYS_CFG, m_LCDC_AXICLK_AUTO_ENABLE | m_W0_AXI_OUTSTANDING2 | m_W1_AXI_OUTSTANDING2,v_LCDC_AXICLK_AUTO_ENABLE(1) | v_W0_AXI_OUTSTANDING2(1) | v_W1_AXI_OUTSTANDING2(1));//eanble axi-clk auto gating for low power LcdWrReg(lcdc_dev,AXI_MS_ID,v_HWC_CHANNEL_ID(5) | v_WIN2_CHANNEL_ID(4) | v_WIN1_YRGB_CHANNEL_ID(3) | v_WIN0_CBR_CHANNEL_ID(2) | v_WIN0_YRGB_CHANNEL_ID(1)); LcdMskReg(lcdc_dev, INT_STATUS,m_HOR_STARTMASK| m_FRM_STARTMASK | m_SCANNING_MASK, v_HOR_STARTMASK(1) | v_FRM_STARTMASK(1) | v_SCANNING_MASK(1)); //mask all interrupt in init LcdMskReg(lcdc_dev,FIFO_WATER_MARK,m_WIN1_FIFO_FULL_LEVEL,v_WIN1_FIFO_FULL_LEVEL(0x1e0)); //LCDC_REG_CFG_DONE(); // write any value to REG_CFG_DONE let config become effective return 0; }