static int vco_set_rate_lpm(struct clk *c, unsigned long rate) { int rc; struct dsi_pll_vco_clk *vco = to_vco_clk(c); struct mdss_pll_resources *dsi_pll_res = vco->priv; rc = mdss_pll_resource_enable(dsi_pll_res, true); if (rc) { pr_err("Failed to enable mdss dsi pll resources\n"); return rc; } /* * DSI PLL software reset. Add HW recommended delays after toggling * the software reset bit off and back on. */ MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01); udelay(1000); MDSS_PLL_REG_W(dsi_pll_res->pll_base, DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00); udelay(1000); rc = vco_set_rate(vco, rate); mdss_pll_resource_enable(dsi_pll_res, false); return rc; }
static int vco_prepare(struct clk *c) { int rc = 0; struct dsi_pll_vco_clk *vco = to_vco_clk(c); struct mdss_pll_resources *dsi_pll_res = vco->priv; if (!dsi_pll_res) { pr_err("Dsi pll resources are not available\n"); return -EINVAL; } if ((dsi_pll_res->vco_cached_rate != 0) && (dsi_pll_res->vco_cached_rate == c->rate)) { rc = vco_set_rate(c, dsi_pll_res->vco_cached_rate); if (rc) { pr_err("vco_set_rate failed. rc=%d\n", rc); goto error; } } rc = dsi_pll_enable(c); error: return rc; }
static int vco_set_rate_hpm(struct clk *c, unsigned long rate) { int rc; struct dsi_pll_vco_clk *vco = to_vco_clk(c); struct mdss_pll_resources *dsi_pll_res = vco->priv; rc = mdss_pll_resource_enable(dsi_pll_res, true); if (rc) { pr_err("Failed to enable mdss dsi pll resources\n"); return rc; } dsi_pll_software_reset(dsi_pll_res); rc = vco_set_rate(vco, rate); mdss_pll_resource_enable(dsi_pll_res, false); return rc; }
static int vco_prepare(struct clk *c) { return vco_set_rate(c, vco_cached_rate); }