static long
i82365write(Chan *c, void *a, long n, vlong off)
{
PCMslot *pp;
char buf[32];
switch(TYPE(c)){
case Qctl:
if(n >= sizeof(buf))
n = sizeof(buf) - 1;
strncpy(buf, a, n);
buf[n] = 0;
pp = slot + SLOTNO(c);
if(!pp->occupied)
error(Eio);
/* set vpp on card */
if(strncmp(buf, "vpp", 3) == 0)
wrreg(pp, Rpc, vcode(atoi(buf+3))|Fautopower|Foutena|Fcardena);
return n;
case Qmem:
case Qattr:
pp = slot + SLOTNO(c);
if(pp->occupied == 0 || pp->enabled == 0)
error(Eio);
n = pcmwrite(pp->slotno, TYPE(c) == Qattr, a, n, off);
if(n < 0)
error(Eio);
return n;
}
error(Ebadarg);
return -1; /* not reached */
}
/*
* configure the PCMslot for IO. We assume very heavily that we can read
* configuration info from the CIS. If not, we won't set up correctly.
*/
static int
pcmio(int slotno, ISAConf *isa)
{
uchar we, x, *p;
PCMslot *pp;
PCMconftab *ct, *et, *t;
PCMmap *m;
int i, index, irq;
char *cp;
irq = isa->irq;
if(irq == 2)
irq = 9;
if(slotno > nslot)
return -1;
pp = slot + slotno;
if(!pp->occupied)
return -1;
et = &pp->ctab[pp->nctab];
ct = 0;
for(i = 0; i < isa->nopt; i++){
if(strncmp(isa->opt[i], "index=", 6))
continue;
index = strtol(&isa->opt[i][6], &cp, 0);
if(cp == &isa->opt[i][6] || index >= pp->nctab)
return -1;
ct = &pp->ctab[index];
}
if(ct == 0){
/* assume default is right */
if(pp->def)
ct = pp->def;
else
ct = pp->ctab;
/* try for best match */
if(ct->nio == 0
|| ct->io[0].start != isa->port || ((1<<irq) & ct->irqs) == 0){
for(t = pp->ctab; t < et; t++)
if(t->nio
&& t->io[0].start == isa->port
&& ((1<<irq) & t->irqs)){
ct = t;
break;
}
}
if(ct->nio == 0 || ((1<<irq) & ct->irqs) == 0){
for(t = pp->ctab; t < et; t++)
if(t->nio && ((1<<irq) & t->irqs)){
ct = t;
break;
}
}
if(ct->nio == 0){
for(t = pp->ctab; t < et; t++)
if(t->nio){
ct = t;
break;
}
}
}
if(ct == et || ct->nio == 0)
return -1;
if(isa->port == 0 && ct->io[0].start == 0)
return -1;
/* route interrupts */
isa->irq = irq;
wrreg(pp, Rigc, irq | Fnotreset | Fiocard);
/* set power and enable device */
x = vcode(ct->vpp1);
wrreg(pp, Rpc, x|Fautopower|Foutena|Fcardena);
/* 16-bit data path */
if(ct->bit16)
x = Ftiming|Fiocs16|Fwidth16;
else
x = Ftiming;
if(ct->nio == 2 && ct->io[1].start)
x |= x<<4;
wrreg(pp, Rio, x);
/*
* enable io port map 0
* the 'top' register value includes the last valid address
*/
if(isa->port == 0)
isa->port = ct->io[0].start;
we = rdreg(pp, Rwe);
wrreg(pp, Riobtm0lo, isa->port);
wrreg(pp, Riobtm0hi, isa->port>>8);
i = isa->port+ct->io[0].len-1;
wrreg(pp, Riotop0lo, i);
wrreg(pp, Riotop0hi, i>>8);
we |= 1<<6;
if(ct->nio >= 2 && ct->io[1].start){
wrreg(pp, Riobtm1lo, ct->io[1].start);
wrreg(pp, Riobtm1hi, ct->io[1].start>>8);
i = ct->io[1].start+ct->io[1].len-1;
wrreg(pp, Riotop1lo, i);
wrreg(pp, Riotop1hi, i>>8);
we |= 1<<7;
}
static void write_vcode(const std::string & vc_img_data)
{
std::ofstream vcode("vercode.jpeg", std::ofstream::out);
vcode.write(vc_img_data.data(), vc_img_data.size());
vcode.close();
}
