static void virgl_flush_frontbuffer(struct pipe_screen *screen, struct pipe_resource *res, unsigned level, unsigned layer, void *winsys_drawable_handle, struct pipe_box *sub_box) { struct virgl_screen *vscreen = virgl_screen(screen); struct virgl_winsys *vws = vscreen->vws; struct virgl_resource *vres = virgl_resource(res); if (vws->flush_frontbuffer) vws->flush_frontbuffer(vws, vres->hw_res, level, layer, winsys_drawable_handle, sub_box); }
int virgl_encoder_set_vertex_buffers(struct virgl_context *ctx, unsigned num_buffers, const struct pipe_vertex_buffer *buffers) { int i; virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_VERTEX_BUFFERS, 0, VIRGL_SET_VERTEX_BUFFERS_SIZE(num_buffers))); for (i = 0; i < num_buffers; i++) { struct virgl_resource *res = virgl_resource(buffers[i].buffer); virgl_encoder_write_dword(ctx->cbuf, buffers[i].stride); virgl_encoder_write_dword(ctx->cbuf, buffers[i].buffer_offset); virgl_encoder_write_res(ctx, res); } return 0; }
int virgl_encoder_set_index_buffer(struct virgl_context *ctx, const struct pipe_index_buffer *ib) { int length = VIRGL_SET_INDEX_BUFFER_SIZE(ib); struct virgl_resource *res = NULL; if (ib) res = virgl_resource(ib->buffer); virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_INDEX_BUFFER, 0, length)); virgl_encoder_write_res(ctx, res); if (ib) { virgl_encoder_write_dword(ctx->cbuf, ib->index_size); virgl_encoder_write_dword(ctx->cbuf, ib->offset); } return 0; }
static void *virgl_buffer_transfer_map(struct pipe_context *ctx, struct pipe_resource *resource, unsigned level, unsigned usage, const struct pipe_box *box, struct pipe_transfer **transfer) { struct virgl_context *vctx = virgl_context(ctx); struct virgl_screen *vs = virgl_screen(ctx->screen); struct virgl_resource *vbuf = virgl_resource(resource); struct virgl_transfer *trans; enum virgl_transfer_map_type map_type; trans = virgl_resource_create_transfer(&vctx->transfer_pool, resource, &vbuf->metadata, level, usage, box); map_type = virgl_resource_transfer_prepare(vctx, trans); switch (map_type) { case VIRGL_TRANSFER_MAP_HW_RES: trans->hw_res_map = vs->vws->resource_map(vs->vws, vbuf->hw_res); break; case VIRGL_TRANSFER_MAP_ERROR: default: trans->hw_res_map = NULL; break; } if (!trans->hw_res_map) { virgl_resource_destroy_transfer(&vctx->transfer_pool, trans); return NULL; } if (usage & PIPE_TRANSFER_WRITE) util_range_add(&vbuf->valid_buffer_range, box->x, box->x + box->width); *transfer = &trans->base; return trans->hw_res_map + trans->offset; }