/* quad for saving/restoring gmem */
void build_quad_vtxbuff(struct adreno_context *drawctxt,
struct gmem_shadow_t *shadow, unsigned int **incmd)
{
unsigned int *cmd = *incmd;
/* quad vertex buffer location (in GPU space) */
shadow->quad_vertices.hostptr = cmd;
shadow->quad_vertices.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
cmd += QUAD_LEN;
/* Used by A3XX, but define for both to make the code easier */
shadow->quad_vertices_restore.hostptr = cmd;
shadow->quad_vertices_restore.gpuaddr =
virt2gpu(cmd, &drawctxt->gpustate);
cmd += QUAD_RESTORE_LEN;
/* tex coord buffer location (in GPU space) */
shadow->quad_texcoords.hostptr = cmd;
shadow->quad_texcoords.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
cmd += TEXCOORD_LEN;
set_gmem_copy_quad(shadow);
*incmd = cmd;
}
void build_quad_vtxbuff(struct adreno_context *drawctxt,
struct gmem_shadow_t *shadow, unsigned int **incmd)
{
unsigned int *cmd = *incmd;
shadow->quad_vertices.hostptr = cmd;
shadow->quad_vertices.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
cmd += QUAD_LEN;
shadow->quad_vertices_restore.hostptr = cmd;
shadow->quad_vertices_restore.gpuaddr =
virt2gpu(cmd, &drawctxt->gpustate);
cmd += QUAD_RESTORE_LEN;
shadow->quad_texcoords.hostptr = cmd;
shadow->quad_texcoords.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
cmd += TEXCOORD_LEN;
set_gmem_copy_quad(shadow);
*incmd = cmd;
}
/* quad for saving/restoring gmem */
void build_quad_vtxbuff(struct adreno_context *drawctxt,
struct gmem_shadow_t *shadow, unsigned int **incmd)
{
unsigned int *cmd = *incmd;
/* quad vertex buffer location (in GPU space) */
shadow->quad_vertices.hostptr = cmd;
shadow->quad_vertices.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
cmd += QUAD_LEN;
/* tex coord buffer location (in GPU space) */
shadow->quad_texcoords.hostptr = cmd;
shadow->quad_texcoords.gpuaddr = virt2gpu(cmd, &drawctxt->gpustate);
cmd += TEXCOORD_LEN;
set_gmem_copy_quad(shadow);
*incmd = cmd;
}
/* chicken restore */
static unsigned int *build_chicken_restore_cmds(
struct adreno_context *drawctxt)
{
unsigned int *start = tmp_ctx.cmd;
unsigned int *cmds = start;
*cmds++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmds++ = 0;
*cmds++ = cp_type0_packet(REG_TP0_CHICKEN, 1);
tmp_ctx.chicken_restore = virt2gpu(cmds, &drawctxt->gpustate);
*cmds++ = 0x00000000;
/* create indirect buffer command for above command sequence */
create_ib1(drawctxt, drawctxt->chicken_restore, start, cmds);
return cmds;
}
static void build_regrestore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *start = tmp_ctx.cmd;
unsigned int *cmd = start;
unsigned int i = 0;
unsigned int reg_array_size = 0;
const unsigned int *ptr_register_ranges;
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
/* H/W Registers */
/* deferred cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, ???); */
cmd++;
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
/* Force mismatch */
*cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1;
#else
*cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
#endif
/* Based on chip id choose the registers ranges*/
if (adreno_is_a220(adreno_dev)) {
ptr_register_ranges = register_ranges_a220;
reg_array_size = ARRAY_SIZE(register_ranges_a220);
} else if (adreno_is_a225(adreno_dev)) {
ptr_register_ranges = register_ranges_a225;
reg_array_size = ARRAY_SIZE(register_ranges_a225);
} else {
ptr_register_ranges = register_ranges_a20x;
reg_array_size = ARRAY_SIZE(register_ranges_a20x);
}
for (i = 0; i < (reg_array_size/2); i++) {
cmd = reg_range(cmd, ptr_register_ranges[i*2],
ptr_register_ranges[i*2+1]);
}
/* Now we know how many register blocks we have, we can compute command
* length
*/
start[2] =
cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, (cmd - start) - 3);
/* Enable shadowing for the entire register block. */
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
start[4] |= (0 << 24) | (4 << 16); /* Disable shadowing. */
#else
start[4] |= (1 << 24) | (4 << 16);
#endif
/* Need to handle some of the registers separately */
*cmd++ = cp_type0_packet(REG_SQ_GPR_MANAGEMENT, 1);
tmp_ctx.reg_values[0] = virt2gpu(cmd, &drawctxt->gpustate);
*cmd++ = 0x00040400;
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
*cmd++ = cp_type0_packet(REG_TP0_CHICKEN, 1);
tmp_ctx.reg_values[1] = virt2gpu(cmd, &drawctxt->gpustate);
*cmd++ = 0x00000000;
if (adreno_is_a22x(adreno_dev)) {
unsigned int i;
unsigned int j = 2;
for (i = REG_A220_VSC_BIN_SIZE; i <=
REG_A220_VSC_PIPE_DATA_LENGTH_7; i++) {
*cmd++ = cp_type0_packet(i, 1);
tmp_ctx.reg_values[j] = virt2gpu(cmd,
&drawctxt->gpustate);
*cmd++ = 0x00000000;
j++;
}
}
/* ALU Constants */
*cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3);
*cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
*cmd++ = (0 << 24) | (0 << 16) | 0; /* Disable shadowing */
#else
*cmd++ = (1 << 24) | (0 << 16) | 0;
#endif
*cmd++ = ALU_CONSTANTS;
/* Texture Constants */
*cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3);
*cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
/* Disable shadowing */
*cmd++ = (0 << 24) | (1 << 16) | 0;
#else
*cmd++ = (1 << 24) | (1 << 16) | 0;
#endif
*cmd++ = TEX_CONSTANTS;
/* Boolean Constants */
*cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + BOOL_CONSTANTS);
*cmd++ = (2 << 16) | 0;
/* the next BOOL_CONSTANT dwords is the shadow area for
* boolean constants.
*/
tmp_ctx.bool_shadow = virt2gpu(cmd, &drawctxt->gpustate);
cmd += BOOL_CONSTANTS;
/* Loop Constants */
*cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + LOOP_CONSTANTS);
*cmd++ = (3 << 16) | 0;
/* the next LOOP_CONSTANTS dwords is the shadow area for
* loop constants.
*/
tmp_ctx.loop_shadow = virt2gpu(cmd, &drawctxt->gpustate);
cmd += LOOP_CONSTANTS;
/* create indirect buffer command for above command sequence */
create_ib1(drawctxt, drawctxt->reg_restore, start, cmd);
tmp_ctx.cmd = cmd;
}
static void
build_shader_save_restore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *save, *restore, *fixup;
unsigned int *startSizeVtx, *startSizePix, *startSizeShared;
unsigned int *partition1;
unsigned int *shaderBases, *partition2;
/* compute vertex, pixel and shared instruction shadow GPU addresses */
tmp_ctx.shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET;
tmp_ctx.shader_pixel = tmp_ctx.shader_vertex
+ _shader_shadow_size(adreno_dev);
tmp_ctx.shader_shared = tmp_ctx.shader_pixel
+ _shader_shadow_size(adreno_dev);
/* restore shader partitioning and instructions */
restore = cmd; /* start address */
/* Invalidate Vertex & Pixel instruction code address and sizes */
*cmd++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
*cmd++ = 0x00000300; /* 0x100 = Vertex, 0x200 = Pixel */
/* Restore previous shader vertex & pixel instruction bases. */
*cmd++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
shaderBases = cmd++; /* TBD #5: shader bases (from fixup) */
/* write the shader partition information to a scratch register */
*cmd++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1);
partition1 = cmd++; /* TBD #4a: partition info (from save) */
/* load vertex shader instructions from the shadow. */
*cmd++ = cp_type3_packet(CP_IM_LOAD, 2);
*cmd++ = tmp_ctx.shader_vertex + 0x0; /* 0x0 = Vertex */
startSizeVtx = cmd++; /* TBD #1: start/size (from save) */
/* load pixel shader instructions from the shadow. */
*cmd++ = cp_type3_packet(CP_IM_LOAD, 2);
*cmd++ = tmp_ctx.shader_pixel + 0x1; /* 0x1 = Pixel */
startSizePix = cmd++; /* TBD #2: start/size (from save) */
/* load shared shader instructions from the shadow. */
*cmd++ = cp_type3_packet(CP_IM_LOAD, 2);
*cmd++ = tmp_ctx.shader_shared + 0x2; /* 0x2 = Shared */
startSizeShared = cmd++; /* TBD #3: start/size (from save) */
/* create indirect buffer command for above command sequence */
create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd);
/*
* fixup SET_SHADER_BASES data
*
* since self-modifying PM4 code is being used here, a seperate
* command buffer is used for this fixup operation, to ensure the
* commands are not read by the PM4 engine before the data fields
* have been written.
*/
fixup = cmd; /* start address */
/* write the shader partition information to a scratch register */
*cmd++ = cp_type0_packet(REG_SCRATCH_REG2, 1);
partition2 = cmd++; /* TBD #4b: partition info (from save) */
/* mask off unused bits, then OR with shader instruction memory size */
*cmd++ = cp_type3_packet(CP_REG_RMW, 3);
*cmd++ = REG_SCRATCH_REG2;
/* AND off invalid bits. */
*cmd++ = 0x0FFF0FFF;
/* OR in instruction memory size. */
*cmd++ = adreno_encode_istore_size(adreno_dev);
/* write the computed value to the SET_SHADER_BASES data field */
*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmd++ = REG_SCRATCH_REG2;
/* TBD #5: shader bases (to restore) */
*cmd++ = virt2gpu(shaderBases, &drawctxt->gpustate);
/* create indirect buffer command for above command sequence */
create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd);
/* save shader partitioning and instructions */
save = cmd; /* start address */
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
/* fetch the SQ_INST_STORE_MANAGMENT register value,
* store the value in the data fields of the SET_CONSTANT commands
* above.
*/
*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmd++ = REG_SQ_INST_STORE_MANAGMENT;
/* TBD #4a: partition info (to restore) */
*cmd++ = virt2gpu(partition1, &drawctxt->gpustate);
*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmd++ = REG_SQ_INST_STORE_MANAGMENT;
/* TBD #4b: partition info (to fixup) */
*cmd++ = virt2gpu(partition2, &drawctxt->gpustate);
/* store the vertex shader instructions */
*cmd++ = cp_type3_packet(CP_IM_STORE, 2);
*cmd++ = tmp_ctx.shader_vertex + 0x0; /* 0x0 = Vertex */
/* TBD #1: start/size (to restore) */
*cmd++ = virt2gpu(startSizeVtx, &drawctxt->gpustate);
/* store the pixel shader instructions */
*cmd++ = cp_type3_packet(CP_IM_STORE, 2);
*cmd++ = tmp_ctx.shader_pixel + 0x1; /* 0x1 = Pixel */
/* TBD #2: start/size (to restore) */
*cmd++ = virt2gpu(startSizePix, &drawctxt->gpustate);
/* store the shared shader instructions if vertex base is nonzero */
*cmd++ = cp_type3_packet(CP_IM_STORE, 2);
*cmd++ = tmp_ctx.shader_shared + 0x2; /* 0x2 = Shared */
/* TBD #3: start/size (to restore) */
*cmd++ = virt2gpu(startSizeShared, &drawctxt->gpustate);
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
/* create indirect buffer command for above command sequence */
create_ib1(drawctxt, drawctxt->shader_save, save, cmd);
tmp_ctx.cmd = cmd;
}
static void build_regrestore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *start = tmp_ctx.cmd;
unsigned int *cmd = start;
unsigned int i = 0;
unsigned int reg_array_size = 0;
const unsigned int *ptr_register_ranges;
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
cmd++;
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
*cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1;
#else
*cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000;
#endif
if (adreno_is_a220(adreno_dev)) {
ptr_register_ranges = register_ranges_a220;
reg_array_size = ARRAY_SIZE(register_ranges_a220);
} else if (adreno_is_a225(adreno_dev)) {
ptr_register_ranges = register_ranges_a225;
reg_array_size = ARRAY_SIZE(register_ranges_a225);
} else {
ptr_register_ranges = register_ranges_a20x;
reg_array_size = ARRAY_SIZE(register_ranges_a20x);
}
for (i = 0; i < (reg_array_size/2); i++) {
cmd = reg_range(cmd, ptr_register_ranges[i*2],
ptr_register_ranges[i*2+1]);
}
start[2] =
cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, (cmd - start) - 3);
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
start[4] |= (0 << 24) | (4 << 16);
#else
start[4] |= (1 << 24) | (4 << 16);
#endif
*cmd++ = cp_type0_packet(REG_SQ_GPR_MANAGEMENT, 1);
tmp_ctx.reg_values[0] = virt2gpu(cmd, &drawctxt->gpustate);
*cmd++ = 0x00040400;
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
*cmd++ = cp_type0_packet(REG_TP0_CHICKEN, 1);
tmp_ctx.reg_values[1] = virt2gpu(cmd, &drawctxt->gpustate);
*cmd++ = 0x00000000;
if (adreno_is_a20x(adreno_dev)) {
*cmd++ = cp_type0_packet(REG_RB_BC_CONTROL, 1);
tmp_ctx.reg_values[2] = virt2gpu(cmd, &drawctxt->gpustate);
*cmd++ = 0x00000000;
}
if (adreno_is_a22x(adreno_dev)) {
unsigned int i;
unsigned int j = 2;
for (i = REG_A220_VSC_BIN_SIZE; i <=
REG_A220_VSC_PIPE_DATA_LENGTH_7; i++) {
*cmd++ = cp_type0_packet(i, 1);
tmp_ctx.reg_values[j] = virt2gpu(cmd,
&drawctxt->gpustate);
*cmd++ = 0x00000000;
j++;
}
}
*cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3);
*cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000;
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
*cmd++ = (0 << 24) | (0 << 16) | 0;
#else
*cmd++ = (1 << 24) | (0 << 16) | 0;
#endif
*cmd++ = ALU_CONSTANTS;
*cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3);
*cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000;
#ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES
*cmd++ = (0 << 24) | (1 << 16) | 0;
#else
*cmd++ = (1 << 24) | (1 << 16) | 0;
#endif
*cmd++ = TEX_CONSTANTS;
*cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + BOOL_CONSTANTS);
*cmd++ = (2 << 16) | 0;
tmp_ctx.bool_shadow = virt2gpu(cmd, &drawctxt->gpustate);
cmd += BOOL_CONSTANTS;
*cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + LOOP_CONSTANTS);
*cmd++ = (3 << 16) | 0;
tmp_ctx.loop_shadow = virt2gpu(cmd, &drawctxt->gpustate);
cmd += LOOP_CONSTANTS;
create_ib1(drawctxt, drawctxt->reg_restore, start, cmd);
tmp_ctx.cmd = cmd;
}
static void
build_shader_save_restore_cmds(struct adreno_device *adreno_dev,
struct adreno_context *drawctxt)
{
unsigned int *cmd = tmp_ctx.cmd;
unsigned int *save, *restore, *fixup;
unsigned int *startSizeVtx, *startSizePix, *startSizeShared;
unsigned int *partition1;
unsigned int *shaderBases, *partition2;
tmp_ctx.shader_vertex = drawctxt->gpustate.gpuaddr + SHADER_OFFSET;
tmp_ctx.shader_pixel = tmp_ctx.shader_vertex
+ _shader_shadow_size(adreno_dev);
tmp_ctx.shader_shared = tmp_ctx.shader_pixel
+ _shader_shadow_size(adreno_dev);
restore = cmd;
*cmd++ = cp_type3_packet(CP_INVALIDATE_STATE, 1);
*cmd++ = 0x00000300;
*cmd++ = cp_type3_packet(CP_SET_SHADER_BASES, 1);
shaderBases = cmd++;
*cmd++ = cp_type0_packet(REG_SQ_INST_STORE_MANAGMENT, 1);
partition1 = cmd++;
*cmd++ = cp_type3_packet(CP_IM_LOAD, 2);
*cmd++ = tmp_ctx.shader_vertex + 0x0;
startSizeVtx = cmd++;
*cmd++ = cp_type3_packet(CP_IM_LOAD, 2);
*cmd++ = tmp_ctx.shader_pixel + 0x1;
startSizePix = cmd++;
*cmd++ = cp_type3_packet(CP_IM_LOAD, 2);
*cmd++ = tmp_ctx.shader_shared + 0x2;
startSizeShared = cmd++;
create_ib1(drawctxt, drawctxt->shader_restore, restore, cmd);
/*
* fixup SET_SHADER_BASES data
*
* since self-modifying PM4 code is being used here, a seperate
* command buffer is used for this fixup operation, to ensure the
* commands are not read by the PM4 engine before the data fields
* have been written.
*/
fixup = cmd;
*cmd++ = cp_type0_packet(REG_SCRATCH_REG2, 1);
partition2 = cmd++;
*cmd++ = cp_type3_packet(CP_REG_RMW, 3);
*cmd++ = REG_SCRATCH_REG2;
*cmd++ = 0x0FFF0FFF;
*cmd++ = adreno_encode_istore_size(adreno_dev);
*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmd++ = REG_SCRATCH_REG2;
*cmd++ = virt2gpu(shaderBases, &drawctxt->gpustate);
create_ib1(drawctxt, drawctxt->shader_fixup, fixup, cmd);
save = cmd;
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmd++ = REG_SQ_INST_STORE_MANAGMENT;
*cmd++ = virt2gpu(partition1, &drawctxt->gpustate);
*cmd++ = cp_type3_packet(CP_REG_TO_MEM, 2);
*cmd++ = REG_SQ_INST_STORE_MANAGMENT;
*cmd++ = virt2gpu(partition2, &drawctxt->gpustate);
*cmd++ = cp_type3_packet(CP_IM_STORE, 2);
*cmd++ = tmp_ctx.shader_vertex + 0x0;
*cmd++ = virt2gpu(startSizeVtx, &drawctxt->gpustate);
*cmd++ = cp_type3_packet(CP_IM_STORE, 2);
*cmd++ = tmp_ctx.shader_pixel + 0x1;
*cmd++ = virt2gpu(startSizePix, &drawctxt->gpustate);
*cmd++ = cp_type3_packet(CP_IM_STORE, 2);
*cmd++ = tmp_ctx.shader_shared + 0x2;
*cmd++ = virt2gpu(startSizeShared, &drawctxt->gpustate);
*cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1);
*cmd++ = 0;
create_ib1(drawctxt, drawctxt->shader_save, save, cmd);
tmp_ctx.cmd = cmd;
}
