void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; if (del_timer_sync(&dev_priv->uncore.force_wake_timer)) gen6_force_wake_timer((unsigned long)dev_priv); /* Hold uncore.lock across reset to prevent any register access * with forcewake not set correctly */ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); if (IS_VALLEYVIEW(dev)) vlv_force_wake_reset(dev_priv); else if (IS_GEN6(dev) || IS_GEN7(dev)) __gen6_gt_force_wake_reset(dev_priv); if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) __gen7_gt_force_wake_mt_reset(dev_priv); if (IS_GEN9(dev)) __gen9_gt_force_wake_mt_reset(dev_priv); if (restore) { /* If reset with a user forcewake, try to restore */ unsigned fw = 0; if (IS_VALLEYVIEW(dev)) { if (dev_priv->uncore.fw_rendercount) fw |= FORCEWAKE_RENDER; if (dev_priv->uncore.fw_mediacount) fw |= FORCEWAKE_MEDIA; } else if (IS_GEN9(dev)) { if (dev_priv->uncore.fw_rendercount) fw |= FORCEWAKE_RENDER; if (dev_priv->uncore.fw_mediacount) fw |= FORCEWAKE_MEDIA; if (dev_priv->uncore.fw_blittercount) fw |= FORCEWAKE_BLITTER; } else { if (dev_priv->uncore.forcewake_count) fw = FORCEWAKE_ALL; } if (fw) dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); if (IS_GEN6(dev) || IS_GEN7(dev)) dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; } spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); }
static void intel_uncore_forcewake_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; if (IS_VALLEYVIEW(dev)) { vlv_force_wake_reset(dev_priv); } else if (INTEL_INFO(dev)->gen >= 6) { __gen6_gt_force_wake_reset(dev_priv); if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) __gen6_gt_force_wake_mt_reset(dev_priv); } }