void samsung_lowlevel_init(virtual_addr_t base, u32 baudrate, u32 input_clock) { unsigned int divider; unsigned int temp; unsigned int remainder; /* First, disable everything */ vmm_out_le16((void *)(base + S3C2410_UCON), 0); /* * Set baud rate * * UBRDIV = (UART_CLK / (16 * BAUD_RATE)) - 1 * DIVSLOT = MOD(UART_CLK / BAUD_RATE, 16) */ temp = udiv32(input_clock, baudrate); divider = udiv32(temp, 16) - 1; remainder = umod32(temp, 16); vmm_out_le16((void *)(base + S3C2410_UBRDIV), (u16) divider); vmm_out_8((void *)(base + S3C2443_DIVSLOT), (u8) remainder); /* Set the UART to be 8 bits, 1 stop bit, no parity */ vmm_out_le32((void *)(base + S3C2410_ULCON), S3C2410_LCON_CS8 | S3C2410_LCON_PNONE); /* enable FIFO, set RX and TX trigger */ vmm_out_le32((void *)(base + S3C2410_UFCON), S3C2410_UFCON_DEFAULT); /* enable the UART */ vmm_out_le32((void *)(base + S3C2410_UCON), S3C2410_UCON_DEFAULT); }
void samsung_lowlevel_putc(virtual_addr_t base, u8 ch) { /* Wait until there is space in the FIFO */ while (!samsung_lowlevel_can_putc(base)) ; /* Send the character */ vmm_out_8((void *)(base + S3C2410_UTXH), ch); }
void uart_lowlevel_init(virtual_addr_t base, u32 reg_align, u32 baudrate, u32 input_clock) { u16 bdiv; bdiv = udiv32(input_clock, (16 * baudrate)); /* set DLAB bit */ vmm_out_8((u8 *)REG_UART_LCR(base,reg_align), 0x80); /* set baudrate divisor */ vmm_out_8((u8 *)REG_UART_DLL(base,reg_align), bdiv & 0xFF); /* set baudrate divisor */ vmm_out_8((u8 *)REG_UART_DLM(base,reg_align), (bdiv >> 8) & 0xFF); /* clear DLAB; set 8 bits, no parity */ vmm_out_8((u8 *)REG_UART_LCR(base,reg_align), 0x03); /* disable FIFO */ vmm_out_8((u8 *)REG_UART_FCR(base,reg_align), 0x01); /* no modem control DTR RTS */ vmm_out_8((u8 *)REG_UART_MCR(base,reg_align), 0x00); /* clear line status */ vmm_in_8((u8 *)REG_UART_LSR(base,reg_align)); /* read receive buffer */ vmm_in_8((u8 *)REG_UART_RBR(base,reg_align)); /* set scratchpad */ vmm_out_8((u8 *)REG_UART_SCR(base,reg_align), 0x00); /* set interrupt enable reg */ vmm_out_8((u8 *)REG_UART_IER(base,reg_align), 0x0F); }
void imx_lowlevel_init(virtual_addr_t base, u32 baudrate, u32 input_clock) { unsigned int temp = vmm_readl((void *)(base + UCR1)); #if 0 unsigned int divider; unsigned int remainder; #endif /* First, disable everything */ temp &= ~UCR1_UARTEN; vmm_writel(temp, (void *)base + UCR1); #if 0 /* * Set baud rate * * UBRDIV = (UART_CLK / (16 * BAUD_RATE)) - 1 * DIVSLOT = MOD(UART_CLK / BAUD_RATE, 16) */ temp = udiv32(input_clock, baudrate); divider = udiv32(temp, 16) - 1; remainder = umod32(temp, 16); vmm_out_le16((void *)(base + S3C2410_UBRDIV), (u16) divider); vmm_out_8((void *)(base + S3C2443_DIVSLOT), (u8) remainder); /* Set the UART to be 8 bits, 1 stop bit, no parity */ vmm_out_le32((void *)(base + S3C2410_ULCON), S3C2410_LCON_CS8 | S3C2410_LCON_PNONE); /* enable FIFO, set RX and TX trigger */ vmm_out_le32((void *)(base + S3C2410_UFCON), S3C2410_UFCON_DEFAULT); #else /* enable the UART */ temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; vmm_writel(temp, (void *)(base + UCR1)); #endif }
void uart_lowlevel_putc(virtual_addr_t base, u32 reg_align, u8 ch) { while (!uart_lowlevel_can_putc(base, reg_align)); vmm_out_8((u8 *)REG_UART_THR(base,reg_align), ch); }
void imx_lowlevel_init(virtual_addr_t base, u32 baudrate, u32 input_clock) { unsigned int temp = vmm_readl((void *)(base + UCR1)); #if 0 unsigned int divider; unsigned int remainder; #endif /* First, disable everything */ temp &= ~UCR1_UARTEN; vmm_writel(temp, (void *)base + UCR1); #if 0 /* * Set baud rate * * UBRDIV = (UART_CLK / (16 * BAUD_RATE)) - 1 * DIVSLOT = MOD(UART_CLK / BAUD_RATE, 16) */ temp = udiv32(input_clock, baudrate); divider = udiv32(temp, 16) - 1; remainder = umod32(temp, 16); vmm_out_le16((void *)(base + S3C2410_UBRDIV), (u16) divider); vmm_out_8((void *)(base + S3C2443_DIVSLOT), (u8) remainder); /* Set the UART to be 8 bits, 1 stop bit, no parity */ vmm_out_le32((void *)(base + S3C2410_ULCON), S3C2410_LCON_CS8 | S3C2410_LCON_PNONE); /* enable FIFO, set RX and TX trigger */ vmm_out_le32((void *)(base + S3C2410_UFCON), S3C2410_UFCON_DEFAULT); #else /* disable all UCR2 related interrupts */ temp = vmm_readl((void *)(base + UCR2)); vmm_writel(temp & ~(UCR2_ATEN | UCR2_ESCI | UCR2_RTSEN), (void *)(base + UCR2)); /* disable all UCR3 related interrupts */ temp = vmm_readl((void *)(base + UCR3)); vmm_writel(temp & ~(UCR3_RXDSEN | UCR3_DTREN | UCR3_FRAERREN | UCR3_TIMEOUTEN | UCR3_AIRINTEN | UCR3_AWAKEN | UCR3_DTRDEN), (void *)(base + UCR3)); /* disable all UCR4 related interrupts */ temp = vmm_readl((void *)(base + UCR4)); vmm_writel(temp & ~(UCR4_DREN | UCR4_TCEN | UCR4_ENIRI | UCR4_WKEN | UCR4_BKEN | UCR4_OREN), (void *)(base + UCR4)); /* trigger interrupt when there is 1 by in the RXFIFO */ temp = vmm_readl((void *)(base + UFCR)); vmm_writel((temp & 0xFFC0) | 1, (void *)(base + UFCR)); /* enable the UART and the receive interrupt */ temp = UCR1_RRDYEN | UCR1_UARTEN; vmm_writel(temp, (void *)(base + UCR1)); #endif }