static int ge_restore_reg(unsigned int addr, unsigned int size, unsigned int *ptr) { #ifdef VPU return vpp_restore_reg(addr, size, ptr); #else return 0; #endif }
void scl_resume(int sts) { switch( sts ){ case 0: // restore register vpp_restore_reg(REG_SCL_BASE1_BEGIN,(REG_SCL_BASE1_END-REG_SCL_BASE1_BEGIN),p_scl->reg_bk); vpp_restore_reg(REG_SCL_BASE2_BEGIN,(REG_SCL_BASE2_END-REG_SCL_BASE2_BEGIN),scl_pm_bk2); p_scl->reg_bk = 0; scl_pm_bk2 = 0; break; case 1: // enable module vppif_reg32_write(SCLW_MIF_ENABLE,scl_pm_w_mif); vppif_reg32_write(SCLR_MIF_ENABLE,scl_pm_r_mif1); vppif_reg32_write(SCLR_MIF2_ENABLE,scl_pm_r_mif2); vppif_reg32_write(SCL_ALU_ENABLE,scl_pm_enable); break; case 2: // enable tg vppif_reg32_write(SCL_TG_ENABLE,scl_pm_tg); vpp_mod_set_clock(VPP_MOD_SCL,VPP_FLAG_DISABLE,1); break; default: break; } }
void lvds_resume(int sts) { switch( sts ){ case 0: // restore register vpp_restore_reg(LVDS_BASE_ADDR+0x00,0x18,lvds_pm_bk); /* 0x120 - 0x420 */ lvds_pm_bk = 0; break; case 1: // enable module break; case 2: // enable tg break; default: break; } }
void govm_resume(int sts) { switch( sts ){ case 0: // restore register vpp_restore_reg(REG_GOVM_BEGIN,(REG_GOVM_END-REG_GOVM_BEGIN),p_govm->reg_bk); p_govm->reg_bk = 0; break; case 1: // enable module break; case 2: // enable tg break; default: break; } }
void vppm_resume(int sts) { switch( sts ){ case 0: // restore register vpp_restore_reg(VPP_BASE_ADDR+0x00,0x1c,p_vppm->reg_bk); p_vppm->reg_bk = 0; break; case 1: // enable module break; case 2: // enable tg break; default: break; } }
void govw_resume(int sts) { switch( sts ){ case 0: // restore register vpp_restore_reg(GOVW_BASE_ADDR+0x00,0xCC,p_govw->reg_bk); /* 0x00 - 0xCC */ p_govw->reg_bk = 0; break; case 1: // enable module vppif_reg32_write(GOVW_HD_MIF_ENABLE,govw_pm_enable); break; case 2: // enable tg vppif_reg32_write(GOVW_TG_ENABLE,govw_pm_tg); break; default: break; } }
void govw_resume(int sts) { switch( sts ){ case 0: // restore register vpp_restore_reg(REG_GOVW_BEGIN,(REG_GOVW_END-REG_GOVW_BEGIN),p_govw->reg_bk); p_govw->reg_bk = 0; break; case 1: // enable module vppif_reg32_write(GOVW_HD_MIF_ENABLE,govw_pm_enable); break; case 2: // enable tg vppif_reg32_write(GOVW_TG_ENABLE,govw_pm_tg); vpp_mod_set_clock(VPP_MOD_GOVW,VPP_FLAG_DISABLE,1); break; default: break; } }
void lvds_resume(int sts) { switch (sts) { case 0: /* restore register */ vpp_restore_reg(REG_LVDS_BEGIN, (REG_LVDS_END-REG_LVDS_BEGIN), lvds_pm_bk); lvds_pm_bk = 0; if (lcd_get_lvds_id() != LCD_LVDS_1024x600) lvds_set_power_down(lvds_pd_bk); break; case 1: /* enable module */ break; case 2: /* enable tg */ break; default: break; } }
void wmt_cec_do_resume(void) { vppif_reg32_out(REG_VPP_SWRST2_SEL, 0x1011111); /* disable GPIO function */ vppif_reg32_write(GPIO_BASE_ADDR + 0x40, BIT4, 4, 0); /* GPIO4 disable GPIO out */ vppif_reg32_write(GPIO_BASE_ADDR + 0x80, BIT4, 4, 0); /* GPIO4 disable pull ctrl */ vppif_reg32_write(GPIO_BASE_ADDR + 0x480, BIT4, 4, 0); /* Suspend GPIO output enable */ vppif_reg32_write(GPIO_BASE_ADDR + 0x80, BIT23, 23, 1); /* Suspend GPIO output high */ vppif_reg32_write(GPIO_BASE_ADDR + 0xC0, BIT23, 23, 1); /* Wake3 disable pull ctrl */ vppif_reg32_write(GPIO_BASE_ADDR + 0x480, BIT19, 19, 0); vpp_restore_reg(REG_CEC_BEGIN, (REG_CEC_END - REG_CEC_BEGIN), wmt_cec_pm_bk); wmt_cec_pm_bk = 0; }