static int dt3155_start_acq(struct dt3155_priv *pd) { struct vb2_buffer *vb = pd->curr_buf; dma_addr_t dma_addr; dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); iowrite32(dma_addr, pd->regs + EVEN_DMA_START); iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START); iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE); iowrite32(img_width, pd->regs + ODD_DMA_STRIDE); /* enable interrupts, clear all irq flags */ iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, pd->regs + CSR1); wait_i2c_reg(pd->regs); write_i2c_reg(pd->regs, CONFIG, pd->config); write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); /* start the board */ write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); return 0; /* success */ }
static int dt3155_start_streaming(struct vb2_queue *q, unsigned count) { struct dt3155_priv *pd = vb2_get_drv_priv(q); struct vb2_buffer *vb = &pd->curr_buf->vb2_buf; dma_addr_t dma_addr; pd->sequence = 0; dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0); iowrite32(dma_addr, pd->regs + EVEN_DMA_START); iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START); iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE); iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE); /* enable interrupts, clear all irq flags */ iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, pd->regs + CSR1); wait_i2c_reg(pd->regs); write_i2c_reg(pd->regs, CONFIG, pd->config); write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); /* start the board */ write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); return 0; }