static void wildfire_enable_irq(unsigned int irq) { if (irq < 16) i8259a_enable_irq(irq); spin_lock(&wildfire_irq_lock); set_bit(irq, &cached_irq_mask); wildfire_update_irq_hw(irq); spin_unlock(&wildfire_irq_lock); }
static void wildfire_mask_and_ack_irq(unsigned int irq) { if (irq < 16) i8259a_mask_and_ack_irq(irq); spin_lock(&wildfire_irq_lock); clear_bit(irq, &cached_irq_mask); wildfire_update_irq_hw(irq); spin_unlock(&wildfire_irq_lock); }
static void wildfire_mask_and_ack_irq(struct irq_data *d) { unsigned int irq = d->irq; if (irq < 16) i8259a_mask_and_ack_irq(d); spin_lock(&wildfire_irq_lock); clear_bit(irq, &cached_irq_mask); wildfire_update_irq_hw(irq); spin_unlock(&wildfire_irq_lock); }
static void __init wildfire_init_irq_hw(void) { #if 0 register wildfire_pca * pca = WILDFIRE_pca(0, 0); volatile unsigned long * enable0, * enable1, * enable2, *enable3; volatile unsigned long * target0, * target1, * target2, *target3; enable0 = (unsigned long *) &pca->pca_int[0].enable; enable1 = (unsigned long *) &pca->pca_int[1].enable; enable2 = (unsigned long *) &pca->pca_int[2].enable; enable3 = (unsigned long *) &pca->pca_int[3].enable; target0 = (unsigned long *) &pca->pca_int[0].target; target1 = (unsigned long *) &pca->pca_int[1].target; target2 = (unsigned long *) &pca->pca_int[2].target; target3 = (unsigned long *) &pca->pca_int[3].target; *enable0 = *enable1 = *enable2 = *enable3 = 0; *target0 = (1UL<<8) | WILDFIRE_QBB(0); *target1 = *target2 = *target3 = 0; mb(); *enable0; *enable1; *enable2; *enable3; *target0; *target1; *target2; *target3; #else int i; doing_init_irq_hw = 1; /* Need to update only once for every possible PCA. */ for (i = 0; i < WILDFIRE_NR_IRQS; i+=WILDFIRE_IRQ_PER_PCA) wildfire_update_irq_hw(i); doing_init_irq_hw = 0; #endif }