void setColor(uint8_t color){
	#ifdef MT9D111
		wrReg16(0xF0,1);
	#endif
	switch(color){
		case yuv422:
			#ifdef MT9D111
				wrReg16(0xC6,(1<<15)|(1<<13)|(7<<8)|125);
				wrReg16(0xC8,0);
				wrReg16(0xC6,(1<<15)|(1<<13)|(7<<8)|126);
				wrReg16(0xC8,0);
			#else
				wrSensorRegs8_8(yuv422_ov7670);
			#endif
		break;
		case rgb565:
			#ifdef MT9D111
				wrReg16(0xC6,(1<<15)|(1<<13)|(7<<8)|125);
				wrReg16(0xC8,(1<<5));
				wrReg16(0xC6,(1<<15)|(1<<13)|(7<<8)|126);
				wrReg16(0xC8,(1<<5));
			#else
				wrSensorRegs8_8(rgb565_ov7670);
				{uint8_t temp=rdReg(0x11);
				_delay_ms(1);
				wrReg(0x11,temp);}//accorind to the linux kernel driver rgb565 PCLK needs re-writting
			#endif
		break;
		#ifndef MT9D111
		case bayerRGB:
			wrSensorRegs8_8(bayerRGB_ov7670);
		break;
		#endif
	}
}
void setRes(enum RESOLUTION res){
	switch(res){
		case VGA:
			wrReg(REG_COM3,0);	// REG_COM3
			wrSensorRegs8_8(vga_ov7670);
		break;
		case QVGA:
			wrReg(REG_COM3,4);	// REG_COM3 enable scaling
			wrSensorRegs8_8(qvga_ov7670);
		break;
		case QQVGA:
			wrReg(REG_COM3,4);	// REG_COM3 enable scaling
			wrSensorRegs8_8(qqvga_ov7670);
		break;
	}
}
void setColorSpace(enum COLORSPACE color){
	switch(color){
		case YUV422:
			wrSensorRegs8_8(yuv422_ov7670);
		break;
		case RGB565:
			wrSensorRegs8_8(rgb565_ov7670);
			{uint8_t temp=rdReg(0x11);
			_delay_ms(1);
			wrReg(0x11,temp);}//according to the Linux kernel driver rgb565 PCLK needs rewriting
		break;
		case BAYER_RGB:
			wrSensorRegs8_8(bayerRGB_ov7670);
		break;
	}
}
void setRes(uint8_t res){
	switch(res){
		#ifdef MT9D111
		case svga:
			setMT9D111res(800,600);
		break;
		#endif
		case vga:
			//wrReg(0x11,2);//divider
			#ifdef ov7740
				scalingToggle(0);
			#elif defined MT9D111
				//wrSensorRegs8_16(MT9D111_VGA);
				setMT9D111res(640,480);
			#else
				wrReg(REG_COM3,0);	// REG_COM3
				wrSensorRegs8_8(vga_ov7670);
			#endif
		break;
		case qvga:
			#ifdef ov7740
				scalingToggle(1);
			#elif defined MT9D111
				//wrSensorRegs8_16(MT9D111_QVGA);
				setMT9D111res(320,240);
			#else
				wrReg(0x11,1);//divider
				wrReg(REG_COM3,4);	// REG_COM3 enable scaling
				wrSensorRegs8_8(qvga_ov7670);
			#endif
		break;
		case qqvga:
			#ifdef ov7740
				scalingToggle(1);
			#elif defined MT9D111
				setMT9D111res(160,120);
			#else
				wrReg(0x11,0);//divider
				wrReg(REG_COM3,4);	// REG_COM3 enable scaling
				wrSensorRegs8_8(qqvga_ov7670);
			#endif
	}
}
void camInit(void){
	wrReg(0x12, 0x80);//Reset the camera.
	_delay_ms(100);
	wrSensorRegs8_8(ov7670_default_regs);
	wrReg(REG_COM10,32);//PCLK does not toggle on HBLANK.
}
void initCam(void)
#endif
{
	#ifdef MT9D111
		//_delay_ms(1000);
		//wrSensorRegs8_16P(MT9D111_init);
		//_delay_ms(1000);
		//wrSensorRegs8_16(MT9D111_QVGA);
		//wrSensorRegs8_16(MT9D111_RGB565);
		//wrSensorRegs8_16(default_size_a_list);
		
		//Start off with a soft reset

		
		wrReg16(0xF0,1);//Set to page 1
		wrReg16(0xC3,0x0501);
		wrReg16(0xF0,0);
		wrReg16(0x0D,0x0021);
		wrReg16(0x0D,0);
		_delay_ms(100);//Cannot use i2c for 24 camera cylces this should be way over that.
		waitStateMT9D111(3);
		//wrReg16(0xF0,0);//Set to page 0
		//wrReg16(0x15,(1<<7)|3);
		wrReg16(0xF0,1);//Set to page 1
		//Poll camera until it is ready
		/*wrReg16(0xC6,(1<<13)|(7<<8)|25);//Row speed
		wrReg16(0xC8,3);*/
		wrReg16(0xC6,(1<<15)|(1<<13)|(2<<8)|14);//increase maximum intergration time
		wrReg16(0xc8,128);
		/*wrReg16(0xC6,(1<<15)|(1<<13)|(2<<8)|16);//increase maximum virtual gain
		wrReg16(0xc8,232);
		wrReg16(0xC6,(1<<15)|(1<<13)|(2<<8)|24);//increase maximum gain
		wrReg16(0xc8,224);*/
		wrReg16(0xC6,(1<<13)|(2<<8)|20);//increase maximum pre-lc digital gain
		wrReg16(0xc8,256);
		/*wrReg16(0xC6,(1<<15)|(1<<13)|(7<<8)|67);//gamma contex A
		wrReg16(0xC8,2);
		wrReg16(0xC6,(1<<15)|(1<<13)|(7<<8)|68);//gamma B
		wrReg16(0xC8,2);*/
		//MT9D111Refresh();
		//_delay_ms(1000);
		wrReg16(0xC6,(1<<13)|(7<<8)|107);//Fifo context A
		wrReg16(0xC8,0);
		wrReg16(0xC6,(1<<13)|(7<<8)|114);//Fifo context B
		wrReg16(0xC8,0);
		MT9D111Refresh();
		//_delay_ms(1000);
	#elif defined ov7740
		wrReg(0x12,rdReg(0x12)|1);//RGB mode
		wrReg(0x11,16);//divider
		wrReg(0x55,0);//disable double
		wrReg(0x83,rdReg(0x83)|(1<<2));//RAW 8
	#elif defined ov7670
		wrReg(0x12, 0x80);
		_delay_ms(100);
		if(bayerUse==2){
			wrSensorRegs8_8(OV7670_QVGA);
		}
		else if(bayerUse==1){
			uint16_t n;
			for(n = 0; n < sizeof(reg_init_data);n+=2)
				wrReg(pgm_read_byte_near(reg_init_data+n), pgm_read_byte_near(reg_init_data+n+1));
		}
		else
			wrSensorRegs8_8(ov7670_default_regs);
		if(bayerUse!=2)
			wrReg(0x1e,rdReg(0x1e)|(1<<5));//hflip
		if(bayerUse==1)
			wrReg(REG_COM10,48);
		else
			wrReg(REG_COM10,32);//pclk does not toggle on HBLANK
		wrReg(REG_COM11,98);
	#else
		#error "No sensor selected"
	#endif
}