void W5100Class::init(void) { delay(300); SPI.begin(SPI_CS); #ifdef W5200 // more initila delay is required delay(200); // should be ok with no divider, W5200 support 80Mhz and SAM3X8E is cadenced to 84Mhz.. // Set clock to 84Mhz but this setting NOT work: SPI clock shaping is not good. // SPI.setClockDivider(SPI_CS, 1); // Set clock to 42Mhz SPI.setClockDivider(SPI_CS, 2); #else // Set clock to 4Mhz (W5100 should support up to 14Mhz) SPI.setClockDivider(SPI_CS, 21); #endif SPI.setDataMode(SPI_CS, SPI_MODE0); writeMR(1<<RST); #ifdef W5200 for (int i=0; i<MAX_SOCK_NUM; i++) { write((0x4000 + i * 0x100 + 0x001F), 2); write((0x4000 + i * 0x100 + 0x001E), 2); } #else writeTMSR(0x55); writeRMSR(0x55); #endif for (int i=0; i<MAX_SOCK_NUM; i++) { SBASE[i] = TXBUF_BASE + SSIZE * i; RBASE[i] = RXBUF_BASE + RSIZE * i; } }
void W5100Class::init(void) { delay(300); SPI.begin(SPI_CS); #ifdef W5200 // should be ok with no divider, W5200 support 80Mhz and SAM3X8E is cadenced to 84Mhz.. //have tried with webserver sample and it's ok but require more tests // Set clock to 42Mhz (W5200 should support up to 80Mhz) SPI.setClockDivider(SPI_CS, 2); // Set clock to 4Mhz // SPI.setClockDivider(SPI_CS, 21); #else // Set clock to 4Mhz (W5100 should support up to 14Mhz) SPI.setClockDivider(SPI_CS, 21); #endif SPI.setDataMode(SPI_CS, SPI_MODE0); writeMR(1<<RST); #ifdef W5200 for (int i=0; i<MAX_SOCK_NUM; i++) { write((0x4000 + i * 0x100 + 0x001F), 2); write((0x4000 + i * 0x100 + 0x001E), 2); } #else writeTMSR(0x55); writeRMSR(0x55); #endif for (int i=0; i<MAX_SOCK_NUM; i++) { SBASE[i] = TXBUF_BASE + SSIZE * i; RBASE[i] = RXBUF_BASE + RSIZE * i; } }