/** * pggs_store - Store persistent global general storage (pggs) sysfs attribute * @kobj: Kobject structure * @attr: Kobject attribute structure * @buf: User entered shutdown_scope attribute string * @count: Size of buf * @reg: Register number * * Return: count argument if request succeeds, the corresponding * error code otherwise * * Helper function for storing a pggs register value. */ static ssize_t pggs_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count, u32 reg) { return write_register(buf, count, IOCTL_READ_PGGS, IOCTL_WRITE_PGGS, reg); }
int sparclite_remove_hw_breakpoint (CORE_ADDR addr, int shadow) { CORE_ADDR dcr, dia1, dia2; dcr = read_register (DCR_REGNUM); dia1 = read_register (DIA1_REGNUM); dia2 = read_register (DIA2_REGNUM); if ((dcr & DIA1_ENABLE) && addr == dia1) write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE)); else if ((dcr & DIA2_ENABLE) && addr == dia2) write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE)); else return -1; return 0; }
int sparclite_remove_watchpoint (CORE_ADDR addr, int len, int type) { CORE_ADDR dcr, dda1, dda2; dcr = read_register (DCR_REGNUM); dda1 = read_register (DDA1_REGNUM); dda2 = read_register (DDA2_REGNUM); if ((dcr & DDA1_ENABLE) && addr == dda1) write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE)); else if ((dcr & DDA2_ENABLE) && addr == dda2) write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE)); else return -1; return 0; }
void ni_tio_init_counter(struct ni_gpct *counter) { struct ni_gpct_device *counter_dev = counter->counter_dev; ni_tio_reset_count_and_disarm(counter); /* initialize counter registers */ counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter->counter_index)] = 0x0; write_register(counter, counter_dev->regs[NITIO_Gi_Autoincrement_Reg(counter-> counter_index)], NITIO_Gi_Autoincrement_Reg(counter->counter_index)); ni_tio_set_bits(counter, NITIO_Gi_Command_Reg(counter->counter_index), ~0, Gi_Synchronize_Gate_Bit); ni_tio_set_bits(counter, NITIO_Gi_Mode_Reg(counter->counter_index), ~0, 0); counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = 0x0; write_register(counter, counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)], NITIO_Gi_LoadA_Reg(counter->counter_index)); counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = 0x0; write_register(counter, counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)], NITIO_Gi_LoadB_Reg(counter->counter_index)); ni_tio_set_bits(counter, NITIO_Gi_Input_Select_Reg(counter->counter_index), ~0, 0); if (ni_tio_counting_mode_registers_present(counter_dev)) { ni_tio_set_bits(counter, NITIO_Gi_Counting_Mode_Reg(counter->counter_index), ~0, 0); } if (ni_tio_second_gate_registers_present(counter_dev)) { counter_dev->regs[NITIO_Gi_Second_Gate_Reg(counter-> counter_index)] = 0x0; write_register(counter, counter_dev->regs[NITIO_Gi_Second_Gate_Reg(counter-> counter_index)], NITIO_Gi_Second_Gate_Reg(counter->counter_index)); } ni_tio_set_bits(counter, NITIO_Gi_DMA_Config_Reg(counter->counter_index), ~0, 0x0); ni_tio_set_bits(counter, NITIO_Gi_Interrupt_Enable_Reg(counter->counter_index), ~0, 0x0); }
void set_aux_vertical_scaler(__u32 height, __u32 a, __u32 interlace) { __u32 value; value = (((((a << 8) / height) & 0xff) * height + (a * 0xf00)) << 0x14) & 0xfff00000; value |= ((((((a << 8) / height) & 0xff) + 1) * height - (a << 8)) << 8) & 0x000fff00; value |= ((a << 8) / height) & 0x000000ff; write_register(0x100cc, value); value = read_register(0x100c0); while(value != (value = read_register(0x100c0))); value = interlace ? 2 : 0; write_register(0x100c0, (((a << 8) / height) << 8) | value | height); write_register(0x100d4, 0x1050020d | (0x41000 - (a << 0xa))); write_register(0x100d8, 0x20b00107 | (0x82c00 - (a << 0xa))); }
// clear_motion - will cause the Delta_X, Delta_Y, and internal motion registers to be cleared void AP_OpticalFlow_ADNS3080::clear_motion() { write_register(ADNS3080_MOTION_CLEAR,0xFF); // writing anything to this register will clear the sensor's motion registers x = 0; y = 0; dx = 0; dy = 0; _motion = false; }
static void write_registers(int cpunum, char *new_values) { uint32_t new_val; int i; for (i = 0; i < 73; i++) { hexToNum(&new_values, (int*)&new_val, 4); write_register(cpunum, i, new_val); } }
void hardware_hwq(uint16_t where) { switch (hardware[where].type) { case HARDWARE_NONE: break; case HARDWARE_BUILTIN: write_register(REG_A, hardware[where].hw.builtin->id & 0xFFFF); write_register(REG_B, hardware[where].hw.builtin->id >> 16); write_register(REG_C, hardware[where].hw.builtin->version); write_register(REG_X, hardware[where].hw.builtin->mfg & 0xFFFF); write_register(REG_Y, hardware[where].hw.builtin->mfg >> 16); break; case HARDWARE_MODULE: module_cmd(hardware[where].hw.module, "hwq\n", 4); break; default: break; } }
// set_frame_rate_auto - set frame rate to auto (true) or manual (false) void AP_OpticalFlow_ADNS3080::set_frame_rate_auto(bool auto_frame_rate) { uint8_t regVal = read_register(ADNS3080_EXTENDED_CONFIG); hal.scheduler->delay_microseconds(50); if( auto_frame_rate == true ) { // set specific frame period write_register(ADNS3080_FRAME_PERIOD_MAX_BOUND_LOWER,0xE0); hal.scheduler->delay_microseconds(50); write_register(ADNS3080_FRAME_PERIOD_MAX_BOUND_UPPER,0x1A); hal.scheduler->delay_microseconds(50); // decide what value to update in extended config regVal = (regVal & ~0x01); }else{ // decide what value to update in extended config regVal = (regVal & ~0x01) | 0x01; } write_register(ADNS3080_EXTENDED_CONFIG, regVal); }
// set_frame_rate_auto - set frame rate to auto (true) or manual (false) void AP_OpticalFlow_ADNS3080_APM2::set_frame_rate_auto(bool auto_frame_rate) { byte regVal = read_register(ADNS3080_EXTENDED_CONFIG); delayMicroseconds(SPI3_DELAY); // small delay if( auto_frame_rate == true ) { // set specific frame period write_register(ADNS3080_FRAME_PERIOD_MAX_BOUND_LOWER,0xE0); delayMicroseconds(SPI3_DELAY); // small delay write_register(ADNS3080_FRAME_PERIOD_MAX_BOUND_UPPER,0x1A); delayMicroseconds(SPI3_DELAY); // small delay // decide what value to update in extended config regVal = (regVal & ~0x01); }else{ // decide what value to update in extended config regVal = (regVal & ~0x01) | 0x01; } write_register(ADNS3080_EXTENDED_CONFIG, regVal); }
void lcd_set_display(lcd_t *lcd, uint8_t display, uint8_t cursor, uint8_t cursorblink) { uint8_t byte = DISPLAY; if (display) byte |= EVERYTHING; if (cursor) byte |= CURSOR; if (display) cursorblink |= CURSORBLINK; write_register(lcd, byte, 0, 0); }
int main(int argc, char **argv) { int fd = -1; int idx = 0; int eq, fg, sw; uint8_t data; int mode = MODE_INVALID; printf("===== PI3EQX8908A i2c configuration =====\n"); if (argc == 2 && !strcmp(argv[1], "read")) { mode = MODE_READ; goto START; } if (argc != 4) { print_usage(); return -2; } mode = MODE_WRITE; eq = atoi(argv[1]); fg = atoi(argv[2]); sw = atoi(argv[3]); if (eq < 0 || eq > 15 || fg < 0 || fg > 3 || sw < 0 || sw > 1) { print_usage(); return -3; } data = (uint8_t)((eq << 4) | (fg << 2) | sw); printf("EQ: %d\n", eq); printf("FG: %d\n", fg); printf("SW: %d\n", sw); printf("data = 0x%02x\n\n", data); START: fd = i2cdev_open(I2CDEV_PATH, O_RDWR | O_SYNC); if (fd < 0) { printf("i2cdev_open failed: %s\n", strerror(errno)); return -1; } print_register(fd); if (mode == MODE_WRITE) { for (idx = IDX_A0; idx <= IDX_B3; idx++) write_register(fd, idx, data); print_register(fd); } i2cdev_close(fd); return 0; }
/** * ggs_store - Store global general storage (ggs) sysfs attribute * @kobj: Kobject structure * @attr: Kobject attribute structure * @buf: User entered shutdown_scope attribute string * @count: Size of buf * @reg: Register number * * Return: count argument if request succeeds, the corresponding * error code otherwise * * Helper function for storing a ggs register value. * * For example, the user-space interface for storing a value to the * ggs0 register: * echo 0xFFFFFFFF 0x1234ABCD > /sys/firmware/zynqmp/ggs0 */ static ssize_t ggs_store(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count, u32 reg) { if (!kobj || !attr || !buf || !count || reg >= GSS_NUM_REGS) return -EINVAL; return write_register(buf, count, IOCTL_READ_GGS, IOCTL_WRITE_GGS, reg); }
// set_shutter_speed_auto - set shutter speed to auto (true), or manual (false) void AP_OpticalFlow_ADNS3080::set_shutter_speed_auto(bool auto_shutter_speed) { uint8_t regVal = read_register(ADNS3080_EXTENDED_CONFIG); hal.scheduler->delay_microseconds(50); if( auto_shutter_speed ) { // return shutter speed max to default write_register(ADNS3080_SHUTTER_MAX_BOUND_LOWER,0x8c); hal.scheduler->delay_microseconds(50); write_register(ADNS3080_SHUTTER_MAX_BOUND_UPPER,0x20); hal.scheduler->delay_microseconds(50); // determine value to put into extended config regVal &= ~0x02; }else{ // determine value to put into extended config regVal |= 0x02; } write_register(ADNS3080_EXTENDED_CONFIG, regVal); hal.scheduler->delay_microseconds(50); }
void m68k_pop_frame () { register FRAME frame = get_current_frame (); register CORE_ADDR fp; register int regnum; struct frame_saved_regs fsr; struct frame_info *fi; char raw_buffer[12]; fi = get_frame_info (frame); fp = fi -> frame; get_frame_saved_regs (fi, &fsr); #if defined (HAVE_68881) for (regnum = FP0_REGNUM + 7 ; regnum >= FP0_REGNUM ; regnum--) { if (fsr.regs[regnum]) { read_memory (fsr.regs[regnum], raw_buffer, 12); write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, 12); } } #endif for (regnum = FP_REGNUM - 1 ; regnum >= 0 ; regnum--) { if (fsr.regs[regnum]) { write_register (regnum, read_memory_integer (fsr.regs[regnum], 4)); } } if (fsr.regs[PS_REGNUM]) { write_register (PS_REGNUM, read_memory_integer (fsr.regs[PS_REGNUM], 4)); } write_register (FP_REGNUM, read_memory_integer (fp, 4)); write_register (PC_REGNUM, read_memory_integer (fp + 4, 4)); write_register (SP_REGNUM, fp + 8); flush_cached_frames (); set_current_frame (create_new_frame (read_register (FP_REGNUM), read_pc ())); }
void Radio::stopListening(void) { if (read_register(FEATURE) & _BV(EN_ACK_PAY)) { _delay_us(155); flush_tx(); } write_register(CONFIG, (read_register(CONFIG)) & ~_BV(PRIM_RX)); // for 3 pins solution TX mode is only left with additional powerDown/powerUp cycle. powerDown(); powerUp(); }
bool Radio::txStandBy() { while (!(read_register(FIFO_STATUS) & _BV(TX_EMPTY))) { if (get_status() & _BV(MAX_RT)) { write_register(STATUS, _BV(MAX_RT)); // Non blocking, flush the data. flush_tx(); return 0; } } return 1; }
/*---------------------------------------------------------------------------*/ int16_t cc110x_set_channel(uint8_t channr) { uint8_t state = cc110x_read_status(CC1100_MARCSTATE) & MARC_STATE; if((state != 1) && (channr > MAX_CHANNR)) { return -1; } write_register(CC1100_CHANNR, channr * 10); radio_channel = channr; return radio_channel; }
// set_shutter_speed_auto - set shutter speed to auto (true), or manual (false) void AP_OpticalFlow_ADNS3080_APM2::set_shutter_speed_auto(bool auto_shutter_speed) { byte regVal = read_register(ADNS3080_EXTENDED_CONFIG); delayMicroseconds(SPI3_DELAY); // small delay if( auto_shutter_speed ) { // return shutter speed max to default write_register(ADNS3080_SHUTTER_MAX_BOUND_LOWER,0x8c); delayMicroseconds(SPI3_DELAY); // small delay write_register(ADNS3080_SHUTTER_MAX_BOUND_UPPER,0x20); delayMicroseconds(SPI3_DELAY); // small delay // determine value to put into extended config regVal &= ~0x02; }else{ // determine value to put into extended config regVal |= 0x02; } write_register(ADNS3080_EXTENDED_CONFIG, regVal); delayMicroseconds(SPI3_DELAY); // small delay }
/* * Perform registrations for service output */ static void do_registers(int argc, char *argv[]) { int i; for (i = 1; i < argc; i++) { if (streq(argv[i], "-s")) { write_register(argv[i + 1]); i++; } } }
int main( int argc, char **argv ) { init_devices(); int i, r, g, b; time_t start, end; double elapsed; while (1) { for (i=REG_PWM0; i<=REG_PWM15; i++) { for (r=0; r<=255; r+=10) { //start = time((char *)0); for (g=0; g<=255; g+=10) { for (b=0; b<=255; b+=10) { write_register(ADDR_BLUE, i, b); } write_register(ADDR_GREEN, i, g); } write_register(ADDR_RED, i, r); //end = time((char *)0); //elapsed = (end - start); //printf("Elapsed %f : %5.2f K/s\n", elapsed, (191.25/elapsed)); } write_register(ADDR_RED, i, 0); write_register(ADDR_GREEN, i, 0); write_register(ADDR_BLUE, i, 0); } } cleanup(); }
int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn, unsigned int *data) { struct ni_gpct_device *counter_dev = counter->counter_dev; const unsigned channel = CR_CHAN(insn->chanspec); unsigned load_reg; if (insn->n < 1) return 0; switch (channel) { case 0: /* Unsafe if counter is armed. Should probably check status and return -EBUSY if armed. */ /* Don't disturb load source select, just use whichever load register is already selected. */ load_reg = ni_tio_next_load_register(counter); write_register(counter, data[0], load_reg); ni_tio_set_bits_transient(counter, NITIO_Gi_Command_Reg(counter-> counter_index), 0, 0, Gi_Load_Bit); /* restore state of load reg to whatever the user set last set it to */ write_register(counter, counter_dev->regs[load_reg], load_reg); break; case 1: counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = data[0]; write_register(counter, data[0], NITIO_Gi_LoadA_Reg(counter->counter_index)); break; case 2: counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = data[0]; write_register(counter, data[0], NITIO_Gi_LoadB_Reg(counter->counter_index)); break; default: return -EINVAL; break; } return 0; }
int ni_tio_winsn(struct ni_gpct *counter, struct comedi_insn *insn, unsigned int *data) { struct ni_gpct_device *counter_dev = counter->counter_dev; const unsigned channel = CR_CHAN(insn->chanspec); unsigned load_reg; if (insn->n < 1) return 0; switch (channel) { case 0: load_reg = ni_tio_next_load_register(counter); write_register(counter, data[0], load_reg); ni_tio_set_bits_transient(counter, NITIO_Gi_Command_Reg(counter-> counter_index), 0, 0, Gi_Load_Bit); write_register(counter, counter_dev->regs[load_reg], load_reg); break; case 1: counter_dev->regs[NITIO_Gi_LoadA_Reg(counter->counter_index)] = data[0]; write_register(counter, data[0], NITIO_Gi_LoadA_Reg(counter->counter_index)); break; case 2: counter_dev->regs[NITIO_Gi_LoadB_Reg(counter->counter_index)] = data[0]; write_register(counter, data[0], NITIO_Gi_LoadB_Reg(counter->counter_index)); break; default: return -EINVAL; break; } return 0; }
static void dp8393x_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { dp8393xState *s = opaque; int reg; if ((addr & ((1 << s->it_shift) - 1)) != 0) { return; } reg = addr >> s->it_shift; write_register(s, reg, (uint16_t)val); }
int sparclite_insert_hw_breakpoint (CORE_ADDR addr, int len) { CORE_ADDR dcr; dcr = read_register (DCR_REGNUM); if (!(dcr & DIA1_ENABLE)) { write_register (DIA1_REGNUM, addr); write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE)); } else if (!(dcr & DIA2_ENABLE)) { write_register (DIA2_REGNUM, addr); write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE)); } else return -1; return 0; }
static PDDebugState update(void* user_data, PDAction action, PDReader* reader, PDWriter* writer) { PluginData* plugin = (PluginData*)user_data; plugin->has_updated_registers = false; plugin->has_updated_exception_location = false; on_action(plugin, action); process_events(plugin, reader, writer); update_events(plugin); if (plugin->has_updated_registers) { log_debug("sending registens\n", ""); PDWrite_event_begin(writer, PDEventType_SetRegisters); PDWrite_array_begin(writer, "registers"); write_status_registers(writer, "flags", plugin->regs.flags); write_register(writer, "pc", 2, plugin->regs.pc, 1); write_register(writer, "sp", 1, plugin->regs.sp, 0); write_register(writer, "a", 1, plugin->regs.a, 0); write_register(writer, "x", 1, plugin->regs.x, 0); write_register(writer, "y", 1, plugin->regs.y, 0); PDWrite_array_end(writer); PDWrite_event_end(writer); } if (plugin->has_updated_exception_location) { PDWrite_event_begin(writer, PDEventType_SetExceptionLocation); PDWrite_u64(writer, "address", plugin->regs.pc); PDWrite_u8(writer, "address_size", 2); PDWrite_event_end(writer); } return plugin->state; }
void set_sync_720x480i() { __u32 value = 0; __u32 reg; reg = 0x10014; set_bits(&value, reg, 0, 0, 0); /* A - 0 */ set_bits(&value, reg, 1, 1, 0); /* B - 0 */ set_bits(&value, reg, 2, 2, 1); /* C - 1 */ set_bits(&value, reg, 3, 3, 0); /* D - 0 */ set_bits(&value, reg, 0xf, 6, 0xf4); /* E - 244 */ set_bits(&value, reg, 0x1a, 0x10, 0x2d0); /* F - 720 */ set_bits(&value, reg, 0x1b, 0x1b, 1); /* G - 1 */ set_bits(&value, reg, 0x1c, 0x1c, 1); /* H - 1 */ set_bits(&value, reg, 0x1d, 0x1d, 0); /* I - 0 */ set_bits(&value, reg, 0x1e, 0x1e, 0); /* J - 0 */ write_register(reg, value); reg = 0x10018; value = 0; set_bits(&value, reg, 8, 0, 0xf); /* K - 15 */ set_bits(&value, reg, 9, 9, invert_hsync ? 1 : 0); /* L - 0 */ set_bits(&value, reg, 0xa, 0xa, invert_vsync ? 1 : 0); /* M - 0 */ set_bits(&value, reg, 0x12, 0xc, 0x3f); /* N - 63 */ set_bits(&value, reg, 0x1c, 0x14, 0x38); /* O - 56 */ write_register(reg, value); reg = 0x1001c; value = 0; set_bits(&value, reg, 2, 0, 3); /* P - 3 */ set_bits(&value, reg, 0xb, 4, 0xe); /* Q - 14 */ set_bits(&value, reg, 0x16, 0xc, 0xf3); /* R - 243 */ set_bits(&value, reg, 0x1b, 0x18, 2); /* S - 2 */ set_bits(&value, reg, 0x1c, 0x1c, 0); /* T - 1 */ write_register(reg, value); reg = 0x10020; value = 0; set_bits(&value, reg, 2, 0, 4); /* U - 4 */ set_bits(&value, reg, 0xb, 4, 0xd); /* V - 13 */ set_bits(&value, reg, 0x16, 0xc, 0xf3); /* W - 243 */ set_bits(&value, reg, 0x1b, 0x18, 3); /* X - 3 */ write_register(reg, value); reg = 0x10028; value = 0; set_bits(&value, reg, 0xb, 0, 0x28); /* BB - 40 */ set_bits(&value, reg, 0x18, 0x18, 1); /* CC - 1 */ write_register(reg, value); reg = 0x10024; value = 0; set_bits(&value, reg, 0x15, 0, 5); /* Y - 5 */ set_bits(&value, reg, 0x18, 0x18, 1); /* Z - 1 */ set_bits(&value, reg, 0x1f, 0x1c, 4); /* AA - 4 */ write_register(reg, value); }
/* generic_pop_current_frame calls this function if the current frame isn't a dummy frame. */ static void mn10300_pop_frame_regular (struct frame_info *frame) { int regnum; write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); /* Restore any saved registers. */ for (regnum = 0; regnum < NUM_REGS; regnum++) if (frame->saved_regs[regnum] != 0) { ULONGEST value; value = read_memory_unsigned_integer (frame->saved_regs[regnum], REGISTER_RAW_SIZE (regnum)); write_register (regnum, value); } /* Actually cut back the stack. */ write_register (SP_REGNUM, FRAME_FP (frame)); /* Don't we need to set the PC?!? XXX FIXME. */ }
void Radio::setAutoAck(uint8_t pipe, bool enable) { if (pipe > 6) { return; } uint8_t en_aa = read_register(EN_AA); if (enable) { en_aa |= _BV(pipe); } else { en_aa &= ~_BV(pipe); } write_register(EN_AA, en_aa); }
// set parameter to 400 or 1200 counts per inch void AP_OpticalFlow_ADNS3080::set_resolution(int resolution) { byte regVal = read_register(ADNS3080_CONFIGURATION_BITS); if( resolution == ADNS3080_RESOLUTION_400 ) { regVal &= ~0x10; }else if( resolution == ADNS3080_RESOLUTION_1200) { regVal |= 0x10; } delayMicroseconds(50); // small delay write_register(ADNS3080_CONFIGURATION_BITS, regVal); }