/* set crtc dpms */
static void xilinx_drm_crtc_dpms(struct drm_crtc *base_crtc, int dpms)
{
struct xilinx_drm_crtc *crtc = to_xilinx_crtc(base_crtc);
DRM_DEBUG_KMS("dpms: %d -> %d\n", crtc->dpms, dpms);
if (crtc->dpms == dpms)
return;
crtc->dpms = dpms;
switch (dpms) {
case DRM_MODE_DPMS_ON:
xilinx_drm_plane_dpms(crtc->priv_plane, dpms);
if (crtc->rgb2yuv)
xilinx_rgb2yuv_enable(crtc->rgb2yuv);
if (crtc->cresample)
xilinx_cresample_enable(crtc->cresample);
xilinx_vtc_enable(crtc->vtc);
break;
default:
xilinx_vtc_disable(crtc->vtc);
xilinx_vtc_reset(crtc->vtc);
if (crtc->cresample) {
xilinx_cresample_disable(crtc->cresample);
xilinx_cresample_reset(crtc->cresample);
}
if (crtc->rgb2yuv) {
xilinx_rgb2yuv_disable(crtc->rgb2yuv);
xilinx_rgb2yuv_reset(crtc->rgb2yuv);
}
xilinx_drm_plane_dpms(crtc->priv_plane, dpms);
break;
}
}
/* set plane dpms */
void xilinx_drm_plane_dpms(struct drm_plane *base_plane, int dpms)
{
struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane);
struct xilinx_drm_plane_manager *manager = plane->manager;
unsigned int i;
DRM_DEBUG_KMS("plane->id: %d\n", plane->id);
DRM_DEBUG_KMS("dpms: %d -> %d\n", plane->dpms, dpms);
if (plane->dpms == dpms)
return;
plane->dpms = dpms;
switch (dpms) {
case DRM_MODE_DPMS_ON:
if (manager->dp_sub) {
if (plane->primary) {
xilinx_drm_dp_sub_enable_alpha(manager->dp_sub,
plane->alpha_enable);
xilinx_drm_dp_sub_set_alpha(manager->dp_sub,
plane->alpha);
}
xilinx_drm_dp_sub_layer_enable(manager->dp_sub,
plane->dp_layer);
}
/* start dma engine */
for (i = 0; i < MAX_NUM_SUB_PLANES; i++)
if (plane->dma[i].chan && plane->dma[i].is_active)
dma_async_issue_pending(plane->dma[i].chan);
if (plane->rgb2yuv)
xilinx_rgb2yuv_enable(plane->rgb2yuv);
if (plane->cresample)
xilinx_cresample_enable(plane->cresample);
/* enable osd */
if (manager->osd) {
xilinx_osd_disable_rue(manager->osd);
xilinx_osd_layer_set_priority(plane->osd_layer,
plane->prio);
xilinx_osd_layer_enable_alpha(plane->osd_layer,
plane->alpha_enable);
xilinx_osd_layer_set_alpha(plane->osd_layer,
plane->alpha);
xilinx_osd_layer_enable(plane->osd_layer);
xilinx_osd_enable_rue(manager->osd);
}
break;
default:
/* disable/reset osd */
if (manager->osd) {
xilinx_osd_disable_rue(manager->osd);
xilinx_osd_layer_set_dimension(plane->osd_layer,
0, 0, 0, 0);
xilinx_osd_layer_disable(plane->osd_layer);
xilinx_osd_enable_rue(manager->osd);
}
if (plane->cresample) {
xilinx_cresample_disable(plane->cresample);
xilinx_cresample_reset(plane->cresample);
}
if (plane->rgb2yuv) {
xilinx_rgb2yuv_disable(plane->rgb2yuv);
xilinx_rgb2yuv_reset(plane->rgb2yuv);
}
/* stop dma engine and release descriptors */
for (i = 0; i < MAX_NUM_SUB_PLANES; i++) {
if (plane->dma[i].chan && plane->dma[i].is_active) {
dmaengine_terminate_all(plane->dma[i].chan);
plane->dma[i].is_active = false;
}
}
if (manager->dp_sub)
xilinx_drm_dp_sub_layer_disable(manager->dp_sub,
plane->dp_layer);
break;
}
}
/* set plane dpms */
void xilinx_drm_plane_dpms(struct drm_plane *base_plane, int dpms)
{
struct xilinx_drm_plane *plane = to_xilinx_plane(base_plane);
struct xilinx_drm_plane_manager *manager = plane->manager;
DRM_DEBUG_KMS("plane->id: %d\n", plane->id);
DRM_DEBUG_KMS("dpms: %d -> %d\n", plane->dpms, dpms);
if (plane->dpms == dpms)
return;
plane->dpms = dpms;
switch (dpms) {
case DRM_MODE_DPMS_ON:
/* start dma engine */
dma_async_issue_pending(plane->dma.chan);
if (plane->rgb2yuv)
xilinx_rgb2yuv_enable(plane->rgb2yuv);
if (plane->cresample)
xilinx_cresample_enable(plane->cresample);
/* enable osd */
if (manager->osd) {
xilinx_osd_disable_rue(manager->osd);
xilinx_osd_layer_set_priority(plane->osd_layer,
plane->prio);
xilinx_osd_layer_set_alpha(plane->osd_layer, 1,
plane->alpha);
xilinx_osd_layer_enable(plane->osd_layer);
if (plane->priv) {
/* set background color as black */
xilinx_osd_set_color(manager->osd, 0x0, 0x0,
0x0);
xilinx_osd_enable(manager->osd);
}
xilinx_osd_enable_rue(manager->osd);
}
break;
default:
/* disable/reset osd */
if (manager->osd) {
xilinx_osd_disable_rue(manager->osd);
xilinx_osd_layer_set_dimension(plane->osd_layer,
0, 0, 0, 0);
xilinx_osd_layer_disable(plane->osd_layer);
if (plane->priv)
xilinx_osd_reset(manager->osd);
xilinx_osd_enable_rue(manager->osd);
}
if (plane->cresample) {
xilinx_cresample_disable(plane->cresample);
xilinx_cresample_reset(plane->cresample);
}
if (plane->rgb2yuv) {
xilinx_rgb2yuv_disable(plane->rgb2yuv);
xilinx_rgb2yuv_reset(plane->rgb2yuv);
}
/* stop dma engine and release descriptors */
dmaengine_terminate_all(plane->dma.chan);
break;
}
}
