Example #1
0
/*
 * CPU PMU identification and probing.
 */
static int probe_current_pmu(struct arm_pmu *pmu)
{
	int cpu = get_cpu();
	unsigned long implementor = read_cpuid_implementor();
	unsigned long part_number = read_cpuid_part_number();
	int ret = -ENODEV;

	pr_info("probing PMU on CPU %d\n", cpu);

	/* ARM Ltd CPUs. */
	if (implementor == ARM_CPU_IMP_ARM) {
		switch (part_number) {
		case ARM_CPU_PART_ARM1136:
		case ARM_CPU_PART_ARM1156:
		case ARM_CPU_PART_ARM1176:
			ret = armv6pmu_init(pmu);
			break;
		case ARM_CPU_PART_ARM11MPCORE:
			ret = armv6mpcore_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A8:
			ret = armv7_a8_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A9:
			ret = armv7_a9_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A5:
			ret = armv7_a5_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A15:
			ret = armv7_a15_pmu_init(pmu);
			break;
		case ARM_CPU_PART_CORTEX_A7:
			ret = armv7_a7_pmu_init(pmu);
			break;
		}
	/* Intel CPUs [xscale]. */
	} else if (implementor == ARM_CPU_IMP_INTEL) {
		switch (xscale_cpu_arch_version()) {
		case ARM_CPU_XSCALE_ARCH_V1:
			ret = xscale1pmu_init(pmu);
			break;
		case ARM_CPU_XSCALE_ARCH_V2:
			ret = xscale2pmu_init(pmu);
			break;
		}
	}

	put_cpu();
	return ret;
}
Example #2
0
/*
 * CPU PMU identification and probing.
 */
static int probe_current_pmu(struct arm_pmu *pmu)
{
	int cpu = get_cpu();
	unsigned long cpuid = read_cpuid_id();
	unsigned long implementor = (cpuid & 0xFF000000) >> 24;
	unsigned long part_number = (cpuid & 0xFFF0);
	int ret = -ENODEV;

	pr_info("probing PMU on CPU %d\n", cpu);

	/* ARM Ltd CPUs. */
	if (0x41 == implementor) {
		switch (part_number) {
		case 0xB360:	/* ARM1136 */
		case 0xB560:	/* ARM1156 */
		case 0xB760:	/* ARM1176 */
			ret = armv6pmu_init(pmu);
			break;
		case 0xB020:	/* ARM11mpcore */
			ret = armv6mpcore_pmu_init(pmu);
			break;
		case 0xC080:	/* Cortex-A8 */
			ret = armv7_a8_pmu_init(pmu);
			break;
		case 0xC090:	/* Cortex-A9 */
			ret = armv7_a9_pmu_init(pmu);
			break;
		case 0xC050:	/* Cortex-A5 */
			ret = armv7_a5_pmu_init(pmu);
			break;
		case 0xC0F0:	/* Cortex-A15 */
			ret = armv7_a15_pmu_init(pmu);
			break;
		case 0xC070:	/* Cortex-A7 */
			ret = armv7_a7_pmu_init(pmu);
			break;
		}
	/* Intel CPUs [xscale]. */
	} else if (0x69 == implementor) {
		part_number = (cpuid >> 13) & 0x7;
		switch (part_number) {
		case 1:
			ret = xscale1pmu_init(pmu);
			break;
		case 2:
			ret = xscale2pmu_init(pmu);
			break;
		}
	}
Example #3
0
/*
 * CPU PMU identification and probing.
 */
static int probe_current_pmu(struct arm_pmu *pmu)
{
	int cpu = get_cpu();
	int ret = -ENODEV;

	pr_info("probing PMU on CPU %d\n", cpu);

	switch (read_cpuid_part()) {
	/* ARM Ltd CPUs. */
	case ARM_CPU_PART_ARM1136:
		ret = armv6_1136_pmu_init(pmu);
		break;
	case ARM_CPU_PART_ARM1156:
		ret = armv6_1156_pmu_init(pmu);
		break;
	case ARM_CPU_PART_ARM1176:
		ret = armv6_1176_pmu_init(pmu);
		break;
	case ARM_CPU_PART_ARM11MPCORE:
		ret = armv6mpcore_pmu_init(pmu);
		break;
	case ARM_CPU_PART_CORTEX_A8:
		ret = armv7_a8_pmu_init(pmu);
		break;
	case ARM_CPU_PART_CORTEX_A9:
		ret = armv7_a9_pmu_init(pmu);
		break;

	default:
		if (read_cpuid_implementor() == ARM_CPU_IMP_INTEL) {
			switch (xscale_cpu_arch_version()) {
			case ARM_CPU_XSCALE_ARCH_V1:
				ret = xscale1pmu_init(pmu);
				break;
			case ARM_CPU_XSCALE_ARCH_V2:
				ret = xscale2pmu_init(pmu);
				break;
			}
		}
		break;
	}

	put_cpu();
	return ret;
}