int xtensa_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { XtensaCPU *cpu = XTENSA_CPU(cs); CPUXtensaState *env = &cpu->env; uint32_t tmp; const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; if (n < 0 || n >= env->config->gdb_regmap.num_regs) { return 0; } tmp = ldl_p(mem_buf); switch (reg->type) { case 9: /*pc*/ env->pc = tmp; break; case 1: /*ar*/ env->phys_regs[(reg->targno & 0xff) % env->config->nareg] = tmp; xtensa_sync_window_from_phys(env); break; case 2: /*SR*/ env->sregs[reg->targno & 0xff] = tmp; break; case 3: /*UR*/ env->uregs[reg->targno & 0xff] = tmp; break; case 4: /*f*/ switch (reg->size) { case 4: env->fregs[reg->targno & 0x0f].f32[FP_F32_LOW] = make_float32(tmp); return 4; case 8: env->fregs[reg->targno & 0x0f].f64 = make_float64(tmp); return 8; default: return 0; } case 8: /*a*/ env->regs[reg->targno & 0x0f] = tmp; break; default: qemu_log_mask(LOG_UNIMP, "%s to reg %d of unsupported type %d\n", __func__, n, reg->type); return 0; } return 4; }
static void rotate_window_abs(uint32_t position) { xtensa_sync_phys_from_window(env); env->sregs[WINDOW_BASE] = windowbase_bound(position, env); xtensa_sync_window_from_phys(env); }