void Nes_Vrc7_Apu::load_snapshot( vrc7_snapshot_t const& in )
{
assert( offsetof (vrc7_snapshot_t,delay) == 28 - 1 );
reset();
next_time = in.delay;
write_reg( in.latch );
int i;
for ( i = 0; i < osc_count; ++i )
{
for ( int j = 0; j < 3; ++j )
oscs [i].regs [j] = in.regs [i] [j];
}
for ( i = 0; i < 8; ++i )
{
ym2413_write( opll, 0, i );
ym2413_write( opll, 1, in.inst [i] );
}
for ( i = 0; i < 3; ++i )
{
for ( int j = 0; j < 6; ++j )
{
ym2413_write( opll, 0, 0x10 + i * 0x10 + j );
ym2413_write( opll, 1, oscs [j].regs [i] );
}
}
}
void Opl_Apu::write_data( blip_time_t time, int data )
{
run_until( time );
switch (type_)
{
case type_opll:
case type_msxmusic:
case type_smsfmunit:
case type_vrc7:
ym2413_write( opl, 0, addr );
ym2413_write( opl, 1, data );
break;
case type_opl:
ym3526_write( opl, 0, addr );
ym3526_write( opl, 1, data );
break;
case type_msxaudio:
/*if ( addr >= 7 && addr <= 7 + 11 )
{
unsigned char temp [2] = { addr - 7, data };
fwrite( &temp, 1, 2, logfile );
}*/
y8950_write( opl, 0, addr );
y8950_write( opl, 1, data );
break;
case type_opl2:
ym3812_write( opl, 0, addr );
ym3812_write( opl, 1, data );
break;
}
}
void Nes_Vrc7_Apu::write_data( blip_time_t time, int data )
{
int type = (addr >> 4) - 1;
int chan = addr & 15;
if ( (unsigned) type < 3 && chan < osc_count )
oscs [chan].regs [type] = data;
if ( time > next_time )
run_until( time );
ym2413_write( opll, 0, addr );
ym2413_write( opll, 1, data );
}
//WRITE8_DEVICE_HANDLER( ym2413_w )
void ym2413_w(void *_info, offs_t offset, UINT8 data)
{
//ym2413_state *info = get_safe_token(device);
ym2413_state *info = (ym2413_state *)_info;
switch(info->EMU_CORE)
{
#ifdef ENABLE_ALL_CORES
case EC_MAME:
ym2413_write(info->chip, offset & 1, data);
break;
#endif
case EC_EMU2413:
OPLL_writeIO(info->chip, offset & 1, data);
break;
}
}
static void UpdateVGM(VGM_PBK* vgmPlay, UINT16 Samples)
{
const dword/*32*/ vgmLen = vgmPlay->file->dataLen;
const UINT8* vgmData = vgmPlay->file->data;
const UINT8* VGMPnt;
dword/*32*/ VGMPos;
dword/*32*/ VGMSmplPos;
UINT8 Command;
UINT8 blockType;
dword/*32*/ blockLen;
vgmPlay->pbSmplPos += Samples;
VGMPos = vgmPlay->vgmPos;
VGMSmplPos = vgmPlay->vgmSmplPos;
while(VGMSmplPos < vgmPlay->pbSmplPos && ! vgmPlay->vgmEnd)
{
VGMPnt = &vgmData[VGMPos];
Command = VGMPnt[0x00];
switch(Command & 0xF0)
{
case 0x70: // small delay (1-16 samples)
VGMSmplPos += (Command & 0x0F) + 0x01;
VGMPos += 0x01;
break;
case 0x80: // DAC write + small delay (0-15 samples)
VGMSmplPos += (Command & 0x0F);
VGMPos += 0x01;
break;
case 0x60:
switch(Command)
{
case 0x66: // End Of File
vgmPlay->vgmPos = VGMPos;
vgmPlay->vgmSmplPos = VGMSmplPos;
if (! DoVgmLoop(vgmPlay))
vgmPlay->vgmEnd = 0x01;
VGMPos = vgmPlay->vgmPos;
VGMSmplPos = vgmPlay->vgmSmplPos;
break;
case 0x62: // 1/60s delay
VGMSmplPos += 735;
VGMPos += 0x01;
break;
case 0x63: // 1/50s delay
VGMSmplPos += 882;
VGMPos += 0x01;
break;
case 0x61: // xx Sample Delay
VGMSmplPos += ReadLE16(&VGMPnt[0x01]);
VGMPos += 0x03;
break;
case 0x67: // Data Block (PCM Data Stream)
blockType = VGMPnt[0x02];
blockLen = ReadLE32(&VGMPnt[0x03]);
blockLen &= 0x7FFFFFFF;
VGMPos += 0x07 + blockLen;
break;
case 0x68: // PCM RAM write
VGMPos += 0x0C;
break;
default:
vgmPlay->vgmEnd = 0x01;
break;
}
break;
case 0x50:
if (Command == 0x50)
{
VGMPos += 0x02; // SN76496 write
break;
}
switch(Command)
{
case 0x51: // YM2413 write
ym2413_write(vgmPlay, VGMPnt[0x01], VGMPnt[0x02]);
break;
case 0x5A: // YM3812 write
ym3812_write(vgmPlay, VGMPnt[0x01], VGMPnt[0x02]);
break;
case 0x5B: // YM3526 write
case 0x5C: // Y8950 write
ym3512_write(vgmPlay, VGMPnt[0x01], VGMPnt[0x02]);
break;
case 0x5E: // YMF262 write, port 0
case 0x5F: // YMF262 write, port 1
ymf262_write(vgmPlay, Command & 0x01, VGMPnt[0x01], VGMPnt[0x02]);
break;
}
VGMPos += 0x03;
break;
case 0x30:
VGMPos += 0x02;
break;
case 0x40:
case 0xA0:
case 0xB0:
VGMPos += 0x03;
break;
case 0xC0:
case 0xD0:
VGMPos += 0x04;
break;
case 0xE0:
case 0xF0:
VGMPos += 0x05;
break;
case 0x90:
switch(Command)
{
case 0x90: // DAC Ctrl: Setup Chip
VGMPos += 0x05;
break;
case 0x91: // DAC Ctrl: Set Data
VGMPos += 0x05;
break;
case 0x92: // DAC Ctrl: Set Freq
VGMPos += 0x06;
break;
case 0x93: // DAC Ctrl: Play from Start Pos
VGMPos += 0x0B;
break;
case 0x94: // DAC Ctrl: Stop immediately
VGMPos += 0x02;
break;
case 0x95: // DAC Ctrl: Play Block (small)
VGMPos += 0x05;
break;
default:
vgmPlay->vgmEnd = 0x01;
break;
}
break;
default:
vgmPlay->vgmEnd = 0x01;
return;
}
if (VGMPos >= vgmLen)
vgmPlay->vgmEnd = 0x01;
}
vgmPlay->vgmPos = VGMPos;
vgmPlay->vgmSmplPos = VGMSmplPos;
if (vgmPlay->vgmEnd)
StopPlayback(vgmPlay);
return;
}
void system_load_state(void *fd)
{
int i;
uint8 reg[0x40];
/* Initialize everything */
cpu_reset();
system_reset();
/* Load VDP context */
fread(&vdp, sizeof(t_vdp), 1, fd);
/* Load SMS context */
fread(&sms, sizeof(t_sms), 1, fd);
/* Load Z80 context */
fread(Z80_Context, sizeof(Z80_Regs), 1, fd);
fread(&after_EI, sizeof(int), 1, fd);
/* Load YM2413 registers */
fread(reg, 0x40, 1, fd);
/* Load SN76489 context */
fread(&sn[0], sizeof(t_SN76496), 1, fd);
/* Restore callbacks */
z80_set_irq_callback(sms_irq_callback);
cpu_readmap[0] = cart.rom + 0x0000; /* 0000-3FFF */
cpu_readmap[1] = cart.rom + 0x2000;
cpu_readmap[2] = cart.rom + 0x4000; /* 4000-7FFF */
cpu_readmap[3] = cart.rom + 0x6000;
cpu_readmap[4] = cart.rom + 0x0000; /* 0000-3FFF */
cpu_readmap[5] = cart.rom + 0x2000;
cpu_readmap[6] = sms.ram;
cpu_readmap[7] = sms.ram;
cpu_writemap[0] = sms.dummy;
cpu_writemap[1] = sms.dummy;
cpu_writemap[2] = sms.dummy;
cpu_writemap[3] = sms.dummy;
cpu_writemap[4] = sms.dummy;
cpu_writemap[5] = sms.dummy;
cpu_writemap[6] = sms.ram;
cpu_writemap[7] = sms.ram;
sms_mapper_w(3, sms.fcr[3]);
sms_mapper_w(2, sms.fcr[2]);
sms_mapper_w(1, sms.fcr[1]);
sms_mapper_w(0, sms.fcr[0]);
/* Force full pattern cache update */
is_vram_dirty = 1;
memset(vram_dirty, 1, 0x200);
/* Restore palette */
for(i = 0; i < PALETTE_SIZE; i += 1)
palette_sync(i);
/* Restore sound state */
if(snd.enabled)
{
/* Clear YM2413 context */
OPLL_reset(opll) ;
OPLL_reset_patch(opll,0) ; /* if use default voice data. */
/* Restore rhythm enable first */
ym2413_write(0, 0, 0x0E);
ym2413_write(0, 1, reg[0x0E]);
/* User instrument settings */
for(i = 0x00; i <= 0x07; i += 1)
{
ym2413_write(0, 0, i);
ym2413_write(0, 1, reg[i]);
}
/* Channel frequency */
for(i = 0x10; i <= 0x18; i += 1)
{
ym2413_write(0, 0, i);
ym2413_write(0, 1, reg[i]);
}
/* Channel frequency + ctrl. */
for(i = 0x20; i <= 0x28; i += 1)
{
ym2413_write(0, 0, i);
ym2413_write(0, 1, reg[i]);
}
/* Instrument and volume settings */
for(i = 0x30; i <= 0x38; i += 1)
{
ym2413_write(0, 0, i);
ym2413_write(0, 1, reg[i]);
}
}
}
