static void
zynqslcr_dumpclocks(struct zynqslcr_softc * const sc)
{
enum zynq_clocks clk;
static const char *str[CLK_MAX] = {
"REF ",
"ARM_PLL ",
"DDR_PLL ",
"IO_PLL ",
"CPU_6X4X",
"CPU_3X2X",
"CPU_2X ",
"CPU_1X ",
"DDR_3X ",
"DDR_2X ",
"DDR_DCI ",
"SMC ",
"QSPI ",
"GIGE0 ",
"GIGE1 ",
"SDIO ",
"UART ",
"SPI ",
"CAN ",
"PCAP ",
"DBG ",
"FCLK0 ",
"FCLK1 ",
"FCLK2 ",
"FCLK3 ",
};
printf("%s\n", __func__);
for (clk = CLK_PS; clk < CLK_MAX; clk++)
printf("%s : %4d MHz\n", str[clk], (zynq_get_clock(clk) + 500000) / 1000000);
}
static uint32_t
get_clock_value(struct zynqslcr_softc *sc, enum zynq_clocks base, uint32_t addr)
{
uint32_t reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, addr);
int div0 = __SHIFTOUT(reg, CLK_DIVISOR0);
int div1 = __SHIFTOUT(reg, CLK_DIVISOR1);
uint32_t val = zynq_get_clock(base);
if (div0 > 0)
val /= div0;
if (div1 > 0)
val /= div1;
return val;
}
void zynq_dump_clocks(void)
{
printf("zynq clocks:\n");
printf("\tarm pll %d\n", get_arm_pll_freq());
printf("\tddr pll %d\n", get_ddr_pll_freq());
printf("\tio pll %d\n", get_io_pll_freq());
printf("\tarm clock %d\n", zynq_get_arm_freq());
printf("\tarm timer clock %d\n", zynq_get_arm_timer_freq());
printf("\tcpu6x4x clock %d\n", get_cpu_6x4x_freq());
printf("\tcpu3x2x clock %d\n", get_cpu_3x2x_freq());
printf("\tcpu2x clock %d\n", get_cpu_2x_freq());
printf("\tcpu1x clock %d\n", get_cpu_1x_freq());
printf("peripheral clocks:\n");
for (uint i = 0; i < _PERIPH_MAX; i++) {
printf("\tperiph %d (%s) clock %u\n", i, periph_to_name(i), zynq_get_clock(i));
}
}
uint32_t
zynq_get_clock(enum zynq_clocks name)
{
struct zynqslcr_softc *sc = slcr_softc;
struct zynq7000_clock_info *clk = sc->sc_clk_info;
uint32_t reg;
if (slcr_softc == NULL)
return -1;
switch (name) {
case CLK_PS:
return clk->clk_ps;
case CLK_ARM_PLL:
if (clk->clk_arm_base == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_ARM_PLL_CTRL);
clk->clk_arm_base = __SHIFTOUT(reg, PLL_FDIV) * clk->clk_ps;
}
return clk->clk_arm_base;
case CLK_DDR_PLL:
if (clk->clk_ddr_base == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_DDR_PLL_CTRL);
clk->clk_ddr_base = __SHIFTOUT(reg, PLL_FDIV) * clk->clk_ps;
}
return clk->clk_ddr_base;
case CLK_IO_PLL:
if (clk->clk_io_base == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_IO_PLL_CTRL);
clk->clk_io_base = __SHIFTOUT(reg, PLL_FDIV) * clk->clk_ps;
}
return clk->clk_io_base;
case CLK_CPU_6X4X:
if (clk->clk_cpu_6x4x == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_ARM_CLK_CTRL);
clk->clk_cpu_6x4x = zynq_get_clock(CLK_ARM_PLL) / __SHIFTOUT(reg, CLK_DIVISOR0);
}
return clk->clk_cpu_6x4x;
case CLK_CPU_3X2X:
if (clk->clk_cpu_3x2x == 0)
clk->clk_cpu_3x2x = zynq_get_clock(CLK_CPU_6X4X) / 2;
return clk->clk_cpu_3x2x;
case CLK_CPU_2X:
if (clk->clk_cpu_2x == 0)
clk->clk_cpu_2x = zynq_get_clock(CLK_CPU_6X4X) / 3;
return clk->clk_cpu_2x;
case CLK_CPU_1X:
if (clk->clk_cpu_1x == 0)
clk->clk_cpu_1x = zynq_get_clock(CLK_CPU_6X4X) / 6;
return clk->clk_cpu_1x;
case CLK_DDR_3X:
if (clk->clk_ddr_3x == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_DDR_CLK_CTRL);
clk->clk_ddr_3x = zynq_get_clock(CLK_DDR_PLL) / __SHIFTOUT(reg, CLK_DDR_3XCLK_DIVISO);
}
return clk->clk_ddr_3x;
case CLK_DDR_2X:
if (clk->clk_ddr_2x == 0) {
reg = bus_space_read_4(sc->sc_iot, sc->sc_ioh, SLCR_DDR_CLK_CTRL);
clk->clk_ddr_2x = zynq_get_clock(CLK_DDR_PLL) / __SHIFTOUT(reg, CLK_DDR_2XCLK_DIVISO);
}
return clk->clk_ddr_2x;
case CLK_DDR_DCI:
if (clk->clk_ddr_dci == 0)
clk->clk_ddr_dci = get_clock_value(sc, CLK_DDR_PLL, SLCR_DCI_CLK_CTRL);
return clk->clk_ddr_dci;
case CLK_SMC:
if (clk->clk_smc == 0)
clk->clk_smc = get_clock_value(sc, CLK_IO_PLL, SLCR_SMC_CLK_CTRL);
return clk->clk_smc;
case CLK_QSPI:
if (clk->clk_qspi == 0)
clk->clk_qspi = get_clock_value(sc, CLK_IO_PLL, SLCR_LQSPI_CLK_CTRL);
return clk->clk_qspi;
case CLK_GIGE0:
if (clk->clk_gige0 == 0)
clk->clk_gige0 = get_clock_value(sc, CLK_IO_PLL, SLCR_GEM0_CLK_CTRL);
return clk->clk_gige0;
case CLK_GIGE1:
if (clk->clk_gige1 == 0)
clk->clk_gige1 = get_clock_value(sc, CLK_IO_PLL, SLCR_GEM1_CLK_CTRL);
return clk->clk_gige1;
case CLK_SDIO:
if (clk->clk_sdio == 0)
clk->clk_sdio = get_clock_value(sc, CLK_IO_PLL, SLCR_SDIO_CLK_CTRL);
return clk->clk_sdio;
case CLK_UART:
if (clk->clk_uart == 0)
clk->clk_uart = get_clock_value(sc, CLK_IO_PLL, SLCR_UART_CLK_CTRL);
return clk->clk_uart;
case CLK_SPI:
if (clk->clk_spi == 0)
clk->clk_spi = get_clock_value(sc, CLK_IO_PLL, SLCR_SPI_CLK_CTRL);
return clk->clk_spi;
case CLK_CAN:
if (clk->clk_can == 0)
clk->clk_can = get_clock_value(sc, CLK_IO_PLL, SLCR_CAN_CLK_CTRL);
return clk->clk_can;
case CLK_PCAP:
if (clk->clk_pcap == 0)
clk->clk_pcap = get_clock_value(sc, CLK_IO_PLL, SLCR_PCAP_CLK_CTRL);
return clk->clk_pcap;
case CLK_DBG:
if (clk->clk_dbg == 0)
clk->clk_dbg = get_clock_value(sc, CLK_IO_PLL, SLCR_DBG_CLK_CTRL);
return clk->clk_dbg;
case CLK_FCLK0:
if (clk->clk_fclk0 == 0)
clk->clk_fclk0 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA0_CLK_CTRL);
return clk->clk_fclk0;
case CLK_FCLK1:
if (clk->clk_fclk1 == 0)
clk->clk_fclk1 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA1_CLK_CTRL);
return clk->clk_fclk1;
case CLK_FCLK2:
if (clk->clk_fclk2 == 0)
clk->clk_fclk2 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA2_CLK_CTRL);
return clk->clk_fclk2;
case CLK_FCLK3:
if (clk->clk_fclk3 == 0)
clk->clk_fclk3 = get_clock_value(sc, CLK_IO_PLL, SLCR_FPGA3_CLK_CTRL);
return clk->clk_fclk3;
default:
return -1;
}
}
