static int at91rm9200_eth_open (struct eth_device *edev) { int ret; at91rm9200_GetPhyInterface (& PhyOps); if (!PhyOps.IsPhyConnected (p_mac)) printf ("PHY not connected!!\n\r"); /* MII management start from here */ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { if (!(ret = PhyOps.Init (p_mac))) { printf ("MAC: error during MII initialization\n"); return 0; } } else { printf ("No link\n\r"); return 0; } return 0; }
int eth_init (bd_t * bd) { int ret; int i; uchar enetaddr[6]; p_mac = AT91C_BASE_EMAC; /* PIO Disable Register */ *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK; #ifdef CONFIG_AT91C_USE_RMII *AT91C_PIOB_PDR = AT91C_PB19_ERXCK; *AT91C_PIOB_BSR = AT91C_PB19_ERXCK; #else *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; /* Select B Register */ *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; #endif *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */ p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ /* Init Ehternet buffers */ for (i = 0; i < RBF_FRAMEMAX; i++) { rbfdt[i].addr = (unsigned long)rbf_framebuf[i]; rbfdt[i].size = 0; } rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; rbfp = &rbfdt[0]; eth_getenv_enetaddr("ethaddr", enetaddr); p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16) | (enetaddr[1] << 8) | (enetaddr[0]); p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]); p_mac->EMAC_RBQP = (long) (&rbfdt[0]); p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC) & ~AT91C_EMAC_CLK; #ifdef CONFIG_AT91C_USE_RMII p_mac->EMAC_CFG |= AT91C_EMAC_RMII; #endif #if (AT91C_MASTER_CLOCK > 40000000) /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64; #endif p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE; at91rm9200_GetPhyInterface (& PhyOps); if (!PhyOps.IsPhyConnected (p_mac)) printf ("PHY not connected!!\n\r"); /* MII management start from here */ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { if (!(ret = PhyOps.Init (p_mac))) { printf ("MAC: error during MII initialization\n"); return 0; } } else { printf ("No link\n\r"); return 0; } return 0; }
int eth_init (bd_t * bd) { int ret; int i; p_mac = AT91C_BASE_EMAC; /* PIO Disable Register */ *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK; #if defined(CONFIG_AT91C_USE_RMII) && !defined(CONFIG_CMC_PU2) *AT91C_PIOB_PDR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; /* Select B Register */ *AT91C_PIOB_BSR = AT91C_PB25_EF100 | AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; #endif *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */ p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ /* Init Ehternet buffers */ rbfdt = (rbf_t *) RBF_FRAMEBTD; for (i = 0; i < RBF_FRAMEMAX; i++) { rbfdt[i].addr = RBF_FRAMEBUF + RBF_FRAMELEN * i; rbfdt[i].size = 0; } rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; rbfp = &rbfdt[0]; p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16) | (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]); p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]); p_mac->EMAC_RBQP = (long) (&rbfdt[0]); p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC) & ~AT91C_EMAC_CLK; #ifdef CONFIG_AT91C_USE_RMII p_mac->EMAC_CFG |= AT91C_EMAC_RMII; #endif p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE; at91rm92000_GetPhyInterface (& PhyOps); if (!PhyOps.IsPhyConnected (p_mac)) printf ("PHY not connected!!\n\r"); /* MII management start from here */ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { if (!(ret = PhyOps.Init (p_mac))) { printf ("MAC: error during MII initialization\n"); return 0; } } else { printf ("No link\n\r"); return 0; } return 0; }
int eth_init (bd_t * bd) { int ret; int i; uchar enetaddr[6]; p_mac = AT91C_BASE_EMAC; /* PIO Disable Register */ *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | AT91C_PA7_ETXCK_EREFCK; #ifdef CONFIG_AT91C_USE_RMII *AT91C_PIOB_PDR = AT91C_PB19_ERXCK; *AT91C_PIOB_BSR = AT91C_PB19_ERXCK; #else *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; /* Select B Register */ *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; #endif *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */ p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ /* Init Ethernet buffers */ for (i = 0; i < RBF_FRAMEMAX; i++) { rbfdt[i].addr = (unsigned long)rbf_framebuf[i]; rbfdt[i].size = 0; } rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP; rbfp = &rbfdt[0]; eth_getenv_enetaddr("ethaddr", enetaddr); /* The CSB337 originally used a version of the MicroMonitor bootloader * which saved Ethernet addresses in the "wrong" order. Operating * systems (like Linux) know this, and apply a workaround. Replicate * that MicroMonitor behavior so we avoid needing to make such OS code * care about which bootloader was used. */ if (machine_is_csb337()) { p_mac->EMAC_SA2H = (enetaddr[0] << 8) | (enetaddr[1]); p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16) | (enetaddr[4] << 8) | (enetaddr[5]); } else { p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16) | (enetaddr[1] << 8) | (enetaddr[0]); p_mac->EMAC_SA2H = (enetaddr[5] << 8) | (enetaddr[4]); } p_mac->EMAC_RBQP = (long) (&rbfdt[0]); p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC) & ~AT91C_EMAC_CLK; #ifdef CONFIG_AT91C_USE_RMII p_mac->EMAC_CFG |= AT91C_EMAC_RMII; #endif #if (AT91C_MASTER_CLOCK > 40000000) /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */ p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64; #endif p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE; at91rm9200_GetPhyInterface (& PhyOps); if (!PhyOps.IsPhyConnected (p_mac)) printf ("PHY not connected!!\n\r"); /* MII management start from here */ if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) { if (!(ret = PhyOps.Init (p_mac))) { printf ("MAC: error during MII initialization\n"); return 0; } } else { printf ("No link\n\r"); return 0; } return 0; }