bool SparcAsmParser::
ParseDirective(AsmToken DirectiveID)
{
StringRef IDVal = DirectiveID.getString();
if (IDVal == ".byte")
return parseDirectiveWord(1, DirectiveID.getLoc());
if (IDVal == ".half")
return parseDirectiveWord(2, DirectiveID.getLoc());
if (IDVal == ".word")
return parseDirectiveWord(4, DirectiveID.getLoc());
if (IDVal == ".nword")
return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
if (is64Bit() && IDVal == ".xword")
return parseDirectiveWord(8, DirectiveID.getLoc());
if (IDVal == ".register") {
// For now, ignore .register directive.
Parser.eatToEndOfStatement();
return false;
}
// Let the MC layer to handle other directives.
return true;
}
bool SparcAsmParser::
ParseDirective(AsmToken DirectiveID)
{
StringRef IDVal = DirectiveID.getString();
if (IDVal == ".byte")
return parseDirectiveWord(1, DirectiveID.getLoc());
if (IDVal == ".half")
return parseDirectiveWord(2, DirectiveID.getLoc());
if (IDVal == ".word")
return parseDirectiveWord(4, DirectiveID.getLoc());
if (IDVal == ".nword")
return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
if (is64Bit() && IDVal == ".xword")
return parseDirectiveWord(8, DirectiveID.getLoc());
if (IDVal == ".register") {
// For now, ignore .register directive.
Parser.eatToEndOfStatement();
return false;
}
if (IDVal == ".proc") {
// For compatibility, ignore this directive.
// (It's supposed to be an "optimization" in the Sun assembler)
Parser.eatToEndOfStatement();
return false;
}
// Let the MC layer to handle other directives.
return true;
}
/// ParseDirective parses the PPC specific directives
bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word")
return ParseDirectiveWord(4, DirectiveID.getLoc());
if (IDVal == ".tc")
return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
return true;
}
bool MSP430AsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal.lower() == ".long") {
ParseLiteralValues(4, DirectiveID.getLoc());
} else if (IDVal.lower() == ".word" || IDVal.lower() == ".short") {
ParseLiteralValues(2, DirectiveID.getLoc());
} else if (IDVal.lower() == ".byte") {
ParseLiteralValues(1, DirectiveID.getLoc());
} else if (IDVal.lower() == ".refsym") {
return ParseDirectiveRefSym(DirectiveID);
}
return true;
}
bool MachOAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
SMLoc IDLoc = DirectiveID.getLoc();
// FIXME: This should be driven based on a hash lookup and callback.
if (IDVal == ".section")
return ParseDirectiveDarwinSection();
if (IDVal == ".zerofill")
return ParseDirectiveDarwinZerofill();
if (IDVal == ".desc")
return ParseDirectiveDarwinSymbolDesc();
if (IDVal == ".lsym")
return ParseDirectiveDarwinLsym();
if (IDVal == ".tbss")
return ParseDirectiveDarwinTBSS();
if (IDVal == ".comm")
return ParseDirectiveComm(/*IsLocal=*/false);
if (IDVal == ".lcomm")
return ParseDirectiveComm(/*IsLocal=*/true);
if (IDVal == ".subsections_via_symbols")
return ParseDirectiveDarwinSubsectionsViaSymbols();
if (IDVal == ".dump")
return ParseDirectiveDarwinDumpOrLoad(IDLoc, /*IsDump=*/true);
if (IDVal == ".load")
return ParseDirectiveDarwinDumpOrLoad(IDLoc, /*IsLoad=*/false);
if (!ParseDirectiveSectionSwitch(IDVal))
return false;
// Don't understand directive.
return true;
}
bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".insn")
return ParseDirectiveInsn(DirectiveID.getLoc());
return true;
}
bool ELFAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
SMLoc IDLoc = DirectiveID.getLoc();
if (IDVal == ".local")
return ParseDirectiveLocal();
if (IDVal == ".lcomm")
return ParseDirectiveComm(/*IsLocal=*/true);
if (IDVal == ".comm")
return ParseDirectiveComm(/*IsLocal=*/false);
if (IDVal == ".size")
return ParseDirectiveSize();
if (!ParseDirectiveSectionSwitch(IDVal))
return false;
// Don't understand directive.
return true;
}
int EDDisassembler::parseInst(SmallVectorImpl<MCParsedAsmOperand*> &operands,
SmallVectorImpl<AsmToken> &tokens,
const std::string &str) {
int ret = 0;
switch (Key.Arch) {
default:
return -1;
case Triple::x86:
case Triple::x86_64:
case Triple::arm:
case Triple::thumb:
break;
}
const char *cStr = str.c_str();
MemoryBuffer *buf = MemoryBuffer::getMemBuffer(cStr, cStr + strlen(cStr));
StringRef instName;
SMLoc instLoc;
SourceMgr sourceMgr;
sourceMgr.AddNewSourceBuffer(buf, SMLoc()); // ownership of buf handed over
MCContext context(*AsmInfo);
OwningPtr<MCStreamer> streamer(createNullStreamer(context));
OwningPtr<AsmParser> genericParser(Tgt->createAsmParser(sys::getHostTriple(),
sourceMgr, context,
*streamer, *AsmInfo));
AsmToken OpcodeToken = genericParser->Lex();
AsmToken NextToken = genericParser->Lex(); // consume next token, because specificParser expects us to
if (OpcodeToken.is(AsmToken::Identifier)) {
instName = OpcodeToken.getString();
instLoc = OpcodeToken.getLoc();
if (NextToken.isNot(AsmToken::Eof) &&
genericParser->ParseInstruction(instName, instLoc, operands))
ret = -1;
} else {
ret = -1;
}
ParserMutex.acquire();
if (!ret) {
GenericAsmLexer->setBuffer(buf);
while (SpecificAsmLexer->Lex(),
SpecificAsmLexer->isNot(AsmToken::Eof) &&
SpecificAsmLexer->isNot(AsmToken::EndOfStatement)) {
if (SpecificAsmLexer->is(AsmToken::Error)) {
ret = -1;
break;
}
tokens.push_back(SpecificAsmLexer->getTok());
}
}
ParserMutex.release();
return ret;
}
/// ParseDirective parses the arm specific directives
bool MBlazeAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getIdentifier();
if (IDVal == ".word")
return ParseDirectiveWord(2, DirectiveID.getLoc());
return true;
}
bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
const AsmToken Tok = Parser.getTok();
StartLoc = Tok.getLoc();
EndLoc = Tok.getEndLoc();
const StringRef &RegName = Tok.getString();
RegNo = getRegForName(RegName);
if (RegNo) {
Parser.Lex();
return false;
}
// Match vgprs and sgprs
if (RegName[0] != 's' && RegName[0] != 'v')
return true;
bool IsVgpr = RegName[0] == 'v';
unsigned RegWidth;
unsigned RegIndexInClass;
if (RegName.size() > 1) {
// We have a 32-bit register
RegWidth = 1;
if (RegName.substr(1).getAsInteger(10, RegIndexInClass))
return true;
Parser.Lex();
} else {
// We have a register greater than 32-bits.
int64_t RegLo, RegHi;
Parser.Lex();
if (getLexer().isNot(AsmToken::LBrac))
return true;
Parser.Lex();
if (getParser().parseAbsoluteExpression(RegLo))
return true;
if (getLexer().isNot(AsmToken::Colon))
return true;
Parser.Lex();
if (getParser().parseAbsoluteExpression(RegHi))
return true;
if (getLexer().isNot(AsmToken::RBrac))
return true;
Parser.Lex();
RegWidth = (RegHi - RegLo) + 1;
if (IsVgpr) {
// VGPR registers aren't aligned.
RegIndexInClass = RegLo;
} else {
// SGPR registers are aligned. Max alignment is 4 dwords.
RegIndexInClass = RegLo / std::min(RegWidth, 4u);
}
}
const MCRegisterInfo *TRC = getContext().getRegisterInfo();
unsigned RC = getRegClass(IsVgpr, RegWidth);
if (RegIndexInClass > TRC->getRegClass(RC).getNumRegs())
return true;
RegNo = TRC->getRegClass(RC).getRegister(RegIndexInClass);
return false;
}
