U_32 CfgCodeSelector::genBlock(U_32 numInEdges,
U_32 numOutEdges,
BlockKind blockKind,
BlockCodeSelector& codeSelector,
double cnt)
{
assert(nextNodeId < numNodes);
U_32 nodeId = nextNodeId++;
Node* bb = irManager.getFlowGraph()->createBlockNode();
bb->setExecCount(cnt);
nodes[nodeId] = bb;
InstCodeSelector instCodeSelector(compilationInterface, *this, irManager, bb);
currBlock = bb;
{
codeSelector.genCode(instCodeSelector);
}
currBlock = NULL;
// Set prolog or epilogue node
switch (blockKind) {
case Prolog:
{
// Copy execution count into IA32 CFG prolog node and
// create an edge from IA32 CFG prolog node to optimizer's prolog node
Node* prolog = irManager.getFlowGraph()->getEntryNode();
prolog->setExecCount(cnt);
irManager.getFlowGraph()->addEdge(prolog, bb, 1.0);
break;
}
case Epilog:
{
assert(bb->isEmpty());
break;
}
case InnerBlock:
break; // nothing to do
}
if (instCodeSelector.endsWithSwitch()) {
// Generate an additional node that contains switch dispatch
U_32 numTargets = instCodeSelector.getSwitchNumTargets();
Opnd * switchSrc = instCodeSelector.getSwitchSrc();
genSwitchBlock(bb, numTargets, switchSrc);
}
return nodeId;
}
U_32 IpfCfgCodeSelector::genBlock(U_32 numInEdges,
U_32 numOutEdges,
BlockKind blockKind,
BlockCodeSelector &codeSelector,
double cnt) {
BbNode *node = new(mm) BbNode(mm, opndManager->getNextNodeId(), (U_32)cnt);
nodes.push_back(node);
if(blockKind == Prolog) cfg.setEnterNode(node);
IPF_LOG << endl << " Generate BB node" << node->getId() << endl;
IpfInstCodeSelector ipfInstCodeSelector(cfg, *node, opnds, compilationInterface);
codeSelector.genCode(ipfInstCodeSelector);
return nodes.size()-1;
}
