SDValue Cpu0TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); Cpu0FunctionInfo *FuncInfo = MF.getInfo<Cpu0FunctionInfo>(); DebugLoc dl = Op.getDebugLoc(); SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), getPointerTy()); // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), MachinePointerInfo(SV), false, false, 0); }
bool Cpu0SETargetLowering:: isEligibleForTailCallOptimization(const Cpu0CC &Cpu0CCInfo, unsigned NextStackOffset, const Cpu0FunctionInfo& FI) const { if (!EnableCpu0TailCalls) return false; // Return false if either the callee or caller has a byval argument. if (Cpu0CCInfo.hasByValArg() || FI.hasByvalArg()) return false; // Return true if the callee's argument area is no larger than the // caller's. return NextStackOffset <= FI.getIncomingArgSize(); }
SDValue Cpu0TargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { Cpu0FunctionInfo *FI = DAG.getMachineFunction().getInfo<Cpu0FunctionInfo>(); return DAG.getRegister(FI->getGlobalBaseReg(), Ty); }
static SDValue GetGlobalReg(SelectionDAG &DAG, EVT Ty) { Cpu0FunctionInfo *FI = DAG.getMachineFunction().getInfo<Cpu0FunctionInfo>(); return DAG.getRegister(FI->getGlobalBaseReg(), Ty); }