C++ (Cpp) IBucket::size Examples

Example #1

File: Processor.cpp Project: taiwanese2001/sesc-echang

void Processor::advanceClock()
{
  clockTicks++;
  //  GMSG(!ROB.empty(),"robTop %d Ul %d Us %d Ub %d",ROB.getIdFromTop(0)
  //       ,unresolvedLoad, unresolvedStore, unresolvedBranch);

  // Fetch Stage
	  if (IFID.hasWork() && !IsBusyWaiting()) {
		IBucket *bucket = pipeQ.pipeLine.newItem();
		if( bucket ) {
		  IFID.fetch(bucket);
		}
	  }
	  
	  // ID Stage (insert to instQueue)
	  if (spaceInInstQueue >= FetchWidth) {
		IBucket *bucket = pipeQ.pipeLine.nextItem();
		if( bucket ) {
		  I(!bucket->empty());
		  //      I(bucket->top()->getInst()->getAddr());
	      
		  spaceInInstQueue -= bucket->size();
		  pipeQ.instQueue.push(bucket);
		}else{
		  noFetch2.inc();
		}
	  }else{
		noFetch.inc();
	  }

	  // RENAME Stage
	  if ( !pipeQ.instQueue.empty() ) {
		spaceInInstQueue += issue(pipeQ);
		//    spaceInInstQueue += issue(pipeQ);
	  }
  //transactional region
  while(TMInterface::HasTransfers(getId()))
  {
	  bool isRead, isRequired;
	  VAddr address;
	  size_t accessSize;
	  TMInterface::GetTransferInfo(isRead, isRequired, address, accessSize);
	  CallbackBase* cb = NotifyCompletedTransCB::create(this,getId(),isRead,address);
	  if(getMemorySystem()->getMemoryOS()->insertTransAccess(isRead,isRequired,address,accessSize,cb))
	  {
		  TMInterface::AcceptTransfer();
	  }
	  else
	  {
		  cb->destroy();
		  TMInterface::DenyTransfer();
		  break;
	  }
  } 

  retire();
}

Example #2

File: GPUSMProcessor.cpp Project: khaleghzadeh/esesc

bool GPUSMProcessor::advance_clock(FlodID fid) {

  if (!active) {
    // time to remove from the running queue
    TaskHandler::removeFromRunning(cpu_id);
    return false;
  }

  fetch(fid);

  if (!busy)
    return false;

  clockTicks.inc();
  setWallClock();

  if (unlikely(throttlingRatio>1)) { 
    throttling_cntr++;

    uint32_t skip = ceil(throttlingRatio/getTurboRatioGPU()); 

    if (throttling_cntr < skip) {
      return true;
    }
    throttling_cntr = 1;
  }

  // ID Stage (insert to instQueue)
  if (spaceInInstQueue >= FetchWidth) {
    //MSG("\nFor CPU %d:",getId());
    IBucket *bucket = pipeQ.pipeLine.nextItem();
    if( bucket ) {
      I(!bucket->empty());
      spaceInInstQueue -= bucket->size();
      pipeQ.instQueue.push(bucket);
    }else{
      noFetch2.inc();
    }
  }else{
    noFetch.inc();
  }

  // RENAME Stage
  if ( !pipeQ.instQueue.empty() ) {
    // FIXME: Clear the per PE counter
    spaceInInstQueue += issue(pipeQ);
  }else if (ROB.empty() && rROB.empty()) {
    //I(0);
    // Still busy if we have some in-flight requests
    busy = pipeQ.pipeLine.hasOutstandingItems();
    return true;
  }

  retire();

  return true;
}

Example #3

File: Processor.cpp Project: dilawar/sesc

void Processor::advanceClock()
{
#ifdef TS_STALL
  if (isStall()) return;
#endif  

  clockTicks++;

  //  GMSG(!ROB.empty(),"robTop %d Ul %d Us %d Ub %d",ROB.getIdFromTop(0)
  //       ,unresolvedLoad, unresolvedStore, unresolvedBranch);

  // Fetch Stage
  if (IFID.hasWork() ) {
    IBucket *bucket = pipeQ.pipeLine.newItem();
    if( bucket ) {
      IFID.fetch(bucket);
    }
  }
  
  // ID Stage (insert to instQueue)
  if (spaceInInstQueue >= FetchWidth) {
    IBucket *bucket = pipeQ.pipeLine.nextItem();
    if( bucket ) {
      I(!bucket->empty());
      //      I(bucket->top()->getInst()->getAddr());
      
      spaceInInstQueue -= bucket->size();
      pipeQ.instQueue.push(bucket);
    }else{
      noFetch2.inc();
    }
  }else{
    noFetch.inc();
  }

  // RENAME Stage
  if ( !pipeQ.instQueue.empty() ) {
    spaceInInstQueue += issue(pipeQ);
    //    spaceInInstQueue += issue(pipeQ);
  }
  
  retire();
}