void
JSONSpewer::spewLIR(MIRGraph *mir)
{
if (!fp_)
return;
beginObjectProperty("lir");
beginListProperty("blocks");
for (MBasicBlockIterator i(mir->begin()); i != mir->end(); i++) {
LBlock *block = i->lir();
if (!block)
continue;
beginObject();
integerProperty("number", i->id());
beginListProperty("instructions");
for (size_t p = 0; p < block->numPhis(); p++)
spewLIns(block->getPhi(p));
for (LInstructionIterator ins(block->begin()); ins != block->end(); ins++)
spewLIns(*ins);
endList();
endObject();
}
endList();
endObject();
}
bool
RegisterAllocator::init()
{
if (!insData.init(mir, graph.numInstructions()))
return false;
if (!entryPositions.reserve(graph.numBlocks()) || !exitPositions.reserve(graph.numBlocks()))
return false;
for (size_t i = 0; i < graph.numBlocks(); i++) {
LBlock* block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++)
insData[ins->id()] = *ins;
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi* phi = block->getPhi(j);
insData[phi->id()] = phi;
}
CodePosition entry = block->numPhis() != 0
? CodePosition(block->getPhi(0)->id(), CodePosition::INPUT)
: inputOf(block->firstInstructionWithId());
CodePosition exit = outputOf(block->lastInstructionWithId());
MOZ_ASSERT(block->mir()->id() == i);
entryPositions.infallibleAppend(entry);
exitPositions.infallibleAppend(exit);
}
return true;
}
void
JSONSpewer::spewIntervals(LinearScanAllocator *regalloc)
{
if (!fp_)
return;
beginObjectProperty("intervals");
beginListProperty("blocks");
for (size_t bno = 0; bno < regalloc->graph.numBlocks(); bno++) {
beginObject();
integerProperty("number", bno);
beginListProperty("vregs");
LBlock *lir = regalloc->graph.getBlock(bno);
for (LInstructionIterator ins = lir->begin(); ins != lir->end(); ins++) {
for (size_t k = 0; k < ins->numDefs(); k++) {
VirtualRegister *vreg = ®alloc->vregs[ins->getDef(k)->virtualRegister()];
beginObject();
integerProperty("vreg", vreg->reg());
beginListProperty("intervals");
for (size_t i = 0; i < vreg->numIntervals(); i++) {
LiveInterval *live = vreg->getInterval(i);
if (live->numRanges()) {
beginObject();
property("allocation");
fprintf(fp_, "\"");
LAllocation::PrintAllocation(fp_, live->getAllocation());
fprintf(fp_, "\"");
beginListProperty("ranges");
for (size_t j = 0; j < live->numRanges(); j++) {
beginObject();
integerProperty("start", live->getRange(j)->from.pos());
integerProperty("end", live->getRange(j)->to.pos());
endObject();
}
endList();
endObject();
}
}
endList();
endObject();
}
}
endList();
endObject();
}
endList();
endObject();
}
bool
LiveRangeAllocator<VREG>::init()
{
if (!RegisterAllocator::init())
return false;
liveIn = lir->mir()->allocate<BitSet*>(graph.numBlockIds());
if (!liveIn)
return false;
// Initialize fixed intervals.
for (size_t i = 0; i < AnyRegister::Total; i++) {
AnyRegister reg = AnyRegister::FromCode(i);
LiveInterval *interval = new LiveInterval(0);
interval->setAllocation(LAllocation(reg));
fixedIntervals[i] = interval;
}
fixedIntervalsUnion = new LiveInterval(0);
if (!vregs.init(lir->mir(), graph.numVirtualRegisters()))
return false;
// Build virtual register objects
for (size_t i = 0; i < graph.numBlocks(); i++) {
if (mir->shouldCancel("LSRA create data structures (main loop)"))
return false;
LBlock *block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++) {
for (size_t j = 0; j < ins->numDefs(); j++) {
LDefinition *def = ins->getDef(j);
if (def->policy() != LDefinition::PASSTHROUGH) {
uint32_t reg = def->virtualRegister();
if (!vregs[reg].init(reg, block, *ins, def, /* isTemp */ false))
return false;
}
}
for (size_t j = 0; j < ins->numTemps(); j++) {
LDefinition *def = ins->getTemp(j);
if (def->isBogusTemp())
continue;
if (!vregs[def].init(def->virtualRegister(), block, *ins, def, /* isTemp */ true))
return false;
}
}
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi *phi = block->getPhi(j);
LDefinition *def = phi->getDef(0);
if (!vregs[def].init(phi->id(), block, phi, def, /* isTemp */ false))
return false;
}
}
return true;
}
void
C1Spewer::spewIntervals(FILE *fp, MBasicBlock *block, LinearScanAllocator *regalloc, size_t &nextId)
{
LBlock *lir = block->lir();
if (!lir)
return;
for (size_t i = 0; i < lir->numPhis(); i++)
spewIntervals(fp, regalloc, lir->getPhi(i), nextId);
for (LInstructionIterator ins = lir->begin(); ins != lir->end(); ins++)
spewIntervals(fp, regalloc, *ins, nextId);
}
void
C1Spewer::spewRanges(GenericPrinter& out, MBasicBlock* block, BacktrackingAllocator* regalloc)
{
LBlock* lir = block->lir();
if (!lir)
return;
for (size_t i = 0; i < lir->numPhis(); i++)
spewRanges(out, regalloc, lir->getPhi(i));
for (LInstructionIterator ins = lir->begin(); ins != lir->end(); ins++)
spewRanges(out, regalloc, *ins);
}
bool
StupidAllocator::init()
{
if (!RegisterAllocator::init())
return false;
if (!virtualRegisters.reserve(graph.numVirtualRegisters()))
return false;
for (size_t i = 0; i < graph.numVirtualRegisters(); i++)
virtualRegisters.infallibleAppend(NULL);
for (size_t i = 0; i < graph.numBlocks(); i++) {
LBlock *block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++) {
for (size_t j = 0; j < ins->numDefs(); j++) {
LDefinition *def = ins->getDef(j);
if (def->policy() != LDefinition::PASSTHROUGH)
virtualRegisters[def->virtualRegister()] = def;
}
for (size_t j = 0; j < ins->numTemps(); j++) {
LDefinition *def = ins->getTemp(j);
if (def->isBogusTemp())
continue;
virtualRegisters[def->virtualRegister()] = def;
}
}
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi *phi = block->getPhi(j);
LDefinition *def = phi->getDef(0);
uint32 vreg = def->virtualRegister();
virtualRegisters[vreg] = def;
}
}
// Assign physical registers to the tracked allocation.
{
registerCount = 0;
RegisterSet remainingRegisters(allRegisters_);
while (!remainingRegisters.empty(/* float = */ false))
registers[registerCount++].reg = AnyRegister(remainingRegisters.takeGeneral());
while (!remainingRegisters.empty(/* float = */ true))
registers[registerCount++].reg = AnyRegister(remainingRegisters.takeFloat());
JS_ASSERT(registerCount <= MAX_REGISTERS);
}
return true;
}
bool
StupidAllocator::init()
{
if (!RegisterAllocator::init())
return false;
if (!virtualRegisters.appendN((LDefinition*)nullptr, graph.numVirtualRegisters()))
return false;
for (size_t i = 0; i < graph.numBlocks(); i++) {
LBlock* block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++) {
for (size_t j = 0; j < ins->numDefs(); j++) {
LDefinition* def = ins->getDef(j);
virtualRegisters[def->virtualRegister()] = def;
}
for (size_t j = 0; j < ins->numTemps(); j++) {
LDefinition* def = ins->getTemp(j);
if (def->isBogusTemp())
continue;
virtualRegisters[def->virtualRegister()] = def;
}
}
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi* phi = block->getPhi(j);
LDefinition* def = phi->getDef(0);
uint32_t vreg = def->virtualRegister();
virtualRegisters[vreg] = def;
}
}
// Assign physical registers to the tracked allocation.
{
registerCount = 0;
LiveRegisterSet remainingRegisters(allRegisters_.asLiveSet());
while (!remainingRegisters.emptyGeneral())
registers[registerCount++].reg = AnyRegister(remainingRegisters.takeAnyGeneral());
while (!remainingRegisters.emptyFloat())
registers[registerCount++].reg = AnyRegister(remainingRegisters.takeAnyFloat());
MOZ_ASSERT(registerCount <= MAX_REGISTERS);
}
return true;
}
void
JSONSpewer::spewRanges(BacktrackingAllocator* regalloc)
{
if (!fp_)
return;
beginObjectProperty("ranges");
beginListProperty("blocks");
for (size_t bno = 0; bno < regalloc->graph.numBlocks(); bno++) {
beginObject();
integerProperty("number", bno);
beginListProperty("vregs");
LBlock* lir = regalloc->graph.getBlock(bno);
for (LInstructionIterator ins = lir->begin(); ins != lir->end(); ins++) {
for (size_t k = 0; k < ins->numDefs(); k++) {
uint32_t id = ins->getDef(k)->virtualRegister();
VirtualRegister* vreg = ®alloc->vregs[id];
beginObject();
integerProperty("vreg", id);
beginListProperty("ranges");
for (LiveRange::RegisterLinkIterator iter = vreg->rangesBegin(); iter; iter++) {
LiveRange* range = LiveRange::get(*iter);
beginObject();
property("allocation");
fprintf(fp_, "\"%s\"", range->bundle()->allocation().toString());
integerProperty("start", range->from().bits());
integerProperty("end", range->to().bits());
endObject();
}
endList();
endObject();
}
}
endList();
endObject();
}
endList();
endObject();
}
bool
RegisterAllocator::init()
{
if (!insData.init(mir, graph.numInstructions()))
return false;
for (size_t i = 0; i < graph.numBlocks(); i++) {
LBlock* block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++)
insData[ins->id()] = *ins;
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi* phi = block->getPhi(j);
insData[phi->id()] = phi;
}
}
return true;
}
bool
RegisterAllocator::init()
{
if (!insData.init(lir->mir(), graph.numInstructions()))
return false;
for (size_t i = 0; i < graph.numBlocks(); i++) {
LBlock *block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++)
insData[*ins].init(*ins, block);
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi *phi = block->getPhi(j);
insData[phi].init(phi, block);
}
}
return true;
}
bool
StupidAllocator::go()
{
// This register allocator is intended to be as simple as possible, while
// still being complicated enough to share properties with more complicated
// allocators. Namely, physical registers may be used to carry virtual
// registers across LIR instructions, but not across basic blocks.
//
// This algorithm does not pay any attention to liveness. It is performed
// as a single forward pass through the basic blocks in the program. As
// virtual registers and temporaries are defined they are assigned physical
// registers, evicting existing allocations in an LRU fashion.
// For virtual registers not carried in a register, a canonical spill
// location is used. Each vreg has a different spill location; since we do
// not track liveness we cannot determine that two vregs have disjoint
// lifetimes. Thus, the maximum stack height is the number of vregs (scaled
// by two on 32 bit platforms to allow storing double values).
graph.setLocalSlotCount(DefaultStackSlot(graph.numVirtualRegisters() - 1) + 1);
if (!init())
return false;
for (size_t blockIndex = 0; blockIndex < graph.numBlocks(); blockIndex++) {
LBlock *block = graph.getBlock(blockIndex);
JS_ASSERT(block->mir()->id() == blockIndex);
for (size_t i = 0; i < registerCount; i++)
registers[i].set(MISSING_ALLOCATION);
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction *ins = *iter;
if (ins == *block->rbegin())
syncForBlockEnd(block, ins);
allocateForInstruction(ins);
}
}
return true;
}
// Scan all instructions inside the loop. If any instruction has a use of a
// definition that is defined outside its containing loop, then stack space
// for that definition must be reserved ahead of time. Otherwise, we could
// re-use storage that has been temporarily allocated - see bug 694481.
bool
GreedyAllocator::findLoopCarriedUses(LBlock *backedge)
{
Vector<LBlock *, 4, SystemAllocPolicy> worklist;
MBasicBlock *mheader = backedge->mir()->loopHeaderOfBackedge();
uint32 upperBound = backedge->lastId();
uint32 lowerBound = mheader->lir()->firstId();
IonSpew(IonSpew_RegAlloc, " Finding loop-carried uses.");
for (size_t i = 0; i < mheader->numContainedInLoop(); i++) {
LBlock *block = mheader->getContainedInLoop(i)->lir();
for (LInstructionIterator i = block->begin(); i != block->end(); i++)
findLoopCarriedUses(*i, lowerBound, upperBound);
for (size_t i = 0; i < block->numPhis(); i++)
findLoopCarriedUses(block->getPhi(i), lowerBound, upperBound);
}
IonSpew(IonSpew_RegAlloc, " Done finding loop-carried uses.");
return true;
}
bool
AllocationIntegrityState::check(bool populateSafepoints)
{
MOZ_ASSERT(!instructions.empty());
#ifdef DEBUG
if (JitSpewEnabled(JitSpew_RegAlloc))
dump();
for (size_t blockIndex = 0; blockIndex < graph.numBlocks(); blockIndex++) {
LBlock* block = graph.getBlock(blockIndex);
// Check that all instruction inputs and outputs have been assigned an allocation.
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction* ins = *iter;
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next())
MOZ_ASSERT(!alloc->isUse());
for (size_t i = 0; i < ins->numDefs(); i++) {
LDefinition* def = ins->getDef(i);
MOZ_ASSERT(!def->output()->isUse());
LDefinition oldDef = instructions[ins->id()].outputs[i];
MOZ_ASSERT_IF(oldDef.policy() == LDefinition::MUST_REUSE_INPUT,
*def->output() == *ins->getOperand(oldDef.getReusedInput()));
}
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition* temp = ins->getTemp(i);
MOZ_ASSERT_IF(!temp->isBogusTemp(), temp->output()->isRegister());
LDefinition oldTemp = instructions[ins->id()].temps[i];
MOZ_ASSERT_IF(oldTemp.policy() == LDefinition::MUST_REUSE_INPUT,
*temp->output() == *ins->getOperand(oldTemp.getReusedInput()));
}
}
}
#endif
// Check that the register assignment and move groups preserve the original
// semantics of the virtual registers. Each virtual register has a single
// write (owing to the SSA representation), but the allocation may move the
// written value around between registers and memory locations along
// different paths through the script.
//
// For each use of an allocation, follow the physical value which is read
// backward through the script, along all paths to the value's virtual
// register's definition.
for (size_t blockIndex = 0; blockIndex < graph.numBlocks(); blockIndex++) {
LBlock* block = graph.getBlock(blockIndex);
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction* ins = *iter;
const InstructionInfo& info = instructions[ins->id()];
LSafepoint* safepoint = ins->safepoint();
if (safepoint) {
for (size_t i = 0; i < ins->numTemps(); i++) {
if (ins->getTemp(i)->isBogusTemp())
continue;
uint32_t vreg = info.temps[i].virtualRegister();
LAllocation* alloc = ins->getTemp(i)->output();
if (!checkSafepointAllocation(ins, vreg, *alloc, populateSafepoints))
return false;
}
MOZ_ASSERT_IF(ins->isCall() && !populateSafepoints,
safepoint->liveRegs().emptyFloat() &&
safepoint->liveRegs().emptyGeneral());
}
size_t inputIndex = 0;
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next()) {
LAllocation oldInput = info.inputs[inputIndex++];
if (!oldInput.isUse())
continue;
uint32_t vreg = oldInput.toUse()->virtualRegister();
if (safepoint && !oldInput.toUse()->usedAtStart()) {
if (!checkSafepointAllocation(ins, vreg, **alloc, populateSafepoints))
return false;
}
// Start checking at the previous instruction, in case this
// instruction reuses its input register for an output.
LInstructionReverseIterator riter = block->rbegin(ins);
riter++;
checkIntegrity(block, *riter, vreg, **alloc, populateSafepoints);
while (!worklist.empty()) {
IntegrityItem item = worklist.popCopy();
checkIntegrity(item.block, *item.block->rbegin(), item.vreg, item.alloc, populateSafepoints);
}
}
}
}
return true;
}
void
RegisterAllocator::dumpInstructions()
{
#ifdef DEBUG
fprintf(stderr, "Instructions:\n");
for (size_t blockIndex = 0; blockIndex < graph.numBlocks(); blockIndex++) {
LBlock* block = graph.getBlock(blockIndex);
MBasicBlock* mir = block->mir();
fprintf(stderr, "\nBlock %lu", static_cast<unsigned long>(blockIndex));
for (size_t i = 0; i < mir->numSuccessors(); i++)
fprintf(stderr, " [successor %u]", mir->getSuccessor(i)->id());
fprintf(stderr, "\n");
for (size_t i = 0; i < block->numPhis(); i++) {
LPhi* phi = block->getPhi(i);
fprintf(stderr, "[%u,%u Phi] [def %s]",
inputOf(phi).bits(),
outputOf(phi).bits(),
phi->getDef(0)->toString());
for (size_t j = 0; j < phi->numOperands(); j++)
fprintf(stderr, " [use %s]", phi->getOperand(j)->toString());
fprintf(stderr, "\n");
}
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction* ins = *iter;
fprintf(stderr, "[");
if (ins->id() != 0)
fprintf(stderr, "%u,%u ", inputOf(ins).bits(), outputOf(ins).bits());
fprintf(stderr, "%s]", ins->opName());
if (ins->isMoveGroup()) {
LMoveGroup* group = ins->toMoveGroup();
for (int i = group->numMoves() - 1; i >= 0; i--) {
// Use two printfs, as LAllocation::toString is not reentant.
fprintf(stderr, " [%s", group->getMove(i).from()->toString());
fprintf(stderr, " -> %s]", group->getMove(i).to()->toString());
}
fprintf(stderr, "\n");
continue;
}
for (size_t i = 0; i < ins->numDefs(); i++)
fprintf(stderr, " [def %s]", ins->getDef(i)->toString());
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition* temp = ins->getTemp(i);
if (!temp->isBogusTemp())
fprintf(stderr, " [temp %s]", temp->toString());
}
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next()) {
if (!alloc->isBogus())
fprintf(stderr, " [use %s]", alloc->toString());
}
fprintf(stderr, "\n");
}
}
fprintf(stderr, "\n");
#endif // DEBUG
}
void
AllocationIntegrityState::dump()
{
#ifdef DEBUG
fprintf(stderr, "Register Allocation Integrity State:\n");
for (size_t blockIndex = 0; blockIndex < graph.numBlocks(); blockIndex++) {
LBlock* block = graph.getBlock(blockIndex);
MBasicBlock* mir = block->mir();
fprintf(stderr, "\nBlock %lu", static_cast<unsigned long>(blockIndex));
for (size_t i = 0; i < mir->numSuccessors(); i++)
fprintf(stderr, " [successor %u]", mir->getSuccessor(i)->id());
fprintf(stderr, "\n");
for (size_t i = 0; i < block->numPhis(); i++) {
const InstructionInfo& info = blocks[blockIndex].phis[i];
LPhi* phi = block->getPhi(i);
CodePosition input(block->getPhi(0)->id(), CodePosition::INPUT);
CodePosition output(block->getPhi(block->numPhis() - 1)->id(), CodePosition::OUTPUT);
fprintf(stderr, "[%u,%u Phi] [def %s] ",
input.bits(),
output.bits(),
phi->getDef(0)->toString());
for (size_t j = 0; j < phi->numOperands(); j++)
fprintf(stderr, " [use %s]", info.inputs[j].toString());
fprintf(stderr, "\n");
}
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction* ins = *iter;
const InstructionInfo& info = instructions[ins->id()];
CodePosition input(ins->id(), CodePosition::INPUT);
CodePosition output(ins->id(), CodePosition::OUTPUT);
fprintf(stderr, "[");
if (input != CodePosition::MIN)
fprintf(stderr, "%u,%u ", input.bits(), output.bits());
fprintf(stderr, "%s]", ins->opName());
if (ins->isMoveGroup()) {
LMoveGroup* group = ins->toMoveGroup();
for (int i = group->numMoves() - 1; i >= 0; i--) {
// Use two printfs, as LAllocation::toString is not reentrant.
fprintf(stderr, " [%s", group->getMove(i).from()->toString());
fprintf(stderr, " -> %s]", group->getMove(i).to()->toString());
}
fprintf(stderr, "\n");
continue;
}
for (size_t i = 0; i < ins->numDefs(); i++)
fprintf(stderr, " [def %s]", ins->getDef(i)->toString());
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition* temp = ins->getTemp(i);
if (!temp->isBogusTemp())
fprintf(stderr, " [temp v%u %s]", info.temps[i].virtualRegister(),
temp->toString());
}
size_t index = 0;
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next()) {
fprintf(stderr, " [use %s", info.inputs[index++].toString());
if (!alloc->isConstant())
fprintf(stderr, " %s", alloc->toString());
fprintf(stderr, "]");
}
fprintf(stderr, "\n");
}
}
// Print discovered allocations at the ends of blocks, in the order they
// were discovered.
Vector<IntegrityItem, 20, SystemAllocPolicy> seenOrdered;
seenOrdered.appendN(IntegrityItem(), seen.count());
for (IntegrityItemSet::Enum iter(seen); !iter.empty(); iter.popFront()) {
IntegrityItem item = iter.front();
seenOrdered[item.index] = item;
}
if (!seenOrdered.empty()) {
fprintf(stderr, "Intermediate Allocations:\n");
for (size_t i = 0; i < seenOrdered.length(); i++) {
IntegrityItem item = seenOrdered[i];
fprintf(stderr, " block %u reg v%u alloc %s\n",
item.block->mir()->id(), item.vreg, item.alloc.toString());
}
}
fprintf(stderr, "\n");
#endif
}
bool
AllocationIntegrityState::record()
{
// Ignore repeated record() calls.
if (!instructions.empty())
return true;
if (!instructions.appendN(InstructionInfo(), graph.numInstructions()))
return false;
if (!virtualRegisters.appendN((LDefinition*)nullptr, graph.numVirtualRegisters()))
return false;
if (!blocks.reserve(graph.numBlocks()))
return false;
for (size_t i = 0; i < graph.numBlocks(); i++) {
blocks.infallibleAppend(BlockInfo());
LBlock* block = graph.getBlock(i);
MOZ_ASSERT(block->mir()->id() == i);
BlockInfo& blockInfo = blocks[i];
if (!blockInfo.phis.reserve(block->numPhis()))
return false;
for (size_t j = 0; j < block->numPhis(); j++) {
blockInfo.phis.infallibleAppend(InstructionInfo());
InstructionInfo& info = blockInfo.phis[j];
LPhi* phi = block->getPhi(j);
MOZ_ASSERT(phi->numDefs() == 1);
uint32_t vreg = phi->getDef(0)->virtualRegister();
virtualRegisters[vreg] = phi->getDef(0);
if (!info.outputs.append(*phi->getDef(0)))
return false;
for (size_t k = 0, kend = phi->numOperands(); k < kend; k++) {
if (!info.inputs.append(*phi->getOperand(k)))
return false;
}
}
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction* ins = *iter;
InstructionInfo& info = instructions[ins->id()];
for (size_t k = 0; k < ins->numTemps(); k++) {
if (!ins->getTemp(k)->isBogusTemp()) {
uint32_t vreg = ins->getTemp(k)->virtualRegister();
virtualRegisters[vreg] = ins->getTemp(k);
}
if (!info.temps.append(*ins->getTemp(k)))
return false;
}
for (size_t k = 0; k < ins->numDefs(); k++) {
if (!ins->getDef(k)->isBogusTemp()) {
uint32_t vreg = ins->getDef(k)->virtualRegister();
virtualRegisters[vreg] = ins->getDef(k);
}
if (!info.outputs.append(*ins->getDef(k)))
return false;
}
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next()) {
if (!info.inputs.append(**alloc))
return false;
}
}
}
return seen.init();
}
