static void
PrintDefinition(char* buf, size_t size, const LDefinition& def)
{
char* cursor = buf;
char* end = buf + size;
cursor += JS_snprintf(cursor, end - cursor, "v%u", def.virtualRegister());
cursor += JS_snprintf(cursor, end - cursor, "<%s>", TypeChars[def.type()]);
if (def.policy() == LDefinition::FIXED)
cursor += JS_snprintf(cursor, end - cursor, ":%s", def.output()->toString());
else if (def.policy() == LDefinition::MUST_REUSE_INPUT)
cursor += JS_snprintf(cursor, end - cursor, ":tied(%u)", def.getReusedInput());
}
static void
PrintDefinition(FILE *fp, const LDefinition &def)
{
fprintf(fp, "[%s", TypeChars[def.type()]);
if (def.virtualRegister())
fprintf(fp, ":%d", def.virtualRegister());
if (def.policy() == LDefinition::PRESET) {
fprintf(fp, " (%s)", def.output()->toString());
} else if (def.policy() == LDefinition::MUST_REUSE_INPUT) {
fprintf(fp, " (!)");
} else if (def.policy() == LDefinition::PASSTHROUGH) {
fprintf(fp, " (-)");
}
fprintf(fp, "]");
}
bool
GreedyAllocator::allocateInstruction(LBlock *block, LInstruction *ins)
{
if (!gen->ensureBallast())
return false;
// Reset internal state used for evicting.
reset();
assertValidRegisterState();
// Step 1. Around a call, save all registers used downstream.
if (ins->isCall() && !spillForCall(ins))
return false;
// Step 2. Find all fixed writable registers, adding them to the
// disallow set.
if (!prescanDefinitions(ins))
return false;
// Step 3. For each use, add fixed policies to the disallow set and
// already allocated registers to the discouraged set.
if (!prescanUses(ins))
return false;
// Step 4. Allocate registers for each definition.
if (!allocateDefinitions(ins))
return false;
// Step 5. Allocate temporaries before inputs, since temporaries
// require a register and may have a MUST_REUSE_INPUT policy.
if (!allocateTemporaries(ins))
return false;
// Step 6. Allocate inputs.
if (!allocateInputs(ins))
return false;
// Step 7. Assign fields of a snapshot.
if (ins->snapshot())
informSnapshot(ins);
// Step 8. Free any allocated stack slots.
for (size_t i = 0; i < ins->numDefs(); i++) {
LDefinition *def = ins->getDef(i);
if (def->policy() == LDefinition::PASSTHROUGH)
continue;
killStack(getVirtualRegister(def));
}
// Step 9. If this instruction has a safepoint, fill it with any stack
// slots and registers that are live.
if (ins->safepoint()) {
if (!informSafepoint(ins->safepoint()))
return false;
}
return true;
}
bool
LiveRangeAllocator<VREG>::init()
{
if (!RegisterAllocator::init())
return false;
liveIn = lir->mir()->allocate<BitSet*>(graph.numBlockIds());
if (!liveIn)
return false;
// Initialize fixed intervals.
for (size_t i = 0; i < AnyRegister::Total; i++) {
AnyRegister reg = AnyRegister::FromCode(i);
LiveInterval *interval = new LiveInterval(0);
interval->setAllocation(LAllocation(reg));
fixedIntervals[i] = interval;
}
fixedIntervalsUnion = new LiveInterval(0);
if (!vregs.init(lir->mir(), graph.numVirtualRegisters()))
return false;
// Build virtual register objects
for (size_t i = 0; i < graph.numBlocks(); i++) {
if (mir->shouldCancel("LSRA create data structures (main loop)"))
return false;
LBlock *block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++) {
for (size_t j = 0; j < ins->numDefs(); j++) {
LDefinition *def = ins->getDef(j);
if (def->policy() != LDefinition::PASSTHROUGH) {
uint32_t reg = def->virtualRegister();
if (!vregs[reg].init(reg, block, *ins, def, /* isTemp */ false))
return false;
}
}
for (size_t j = 0; j < ins->numTemps(); j++) {
LDefinition *def = ins->getTemp(j);
if (def->isBogusTemp())
continue;
if (!vregs[def].init(def->virtualRegister(), block, *ins, def, /* isTemp */ true))
return false;
}
}
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi *phi = block->getPhi(j);
LDefinition *def = phi->getDef(0);
if (!vregs[def].init(phi->id(), block, phi, def, /* isTemp */ false))
return false;
}
}
return true;
}
LAllocation *
StupidAllocator::stackLocation(uint32_t vreg)
{
LDefinition *def = virtualRegisters[vreg];
if (def->policy() == LDefinition::PRESET && def->output()->isArgument())
return def->output();
return new LStackSlot(DefaultStackSlot(vreg), def->type() == LDefinition::DOUBLE);
}
LAllocation *
StupidAllocator::stackLocation(uint32_t vreg)
{
LDefinition *def = virtualRegisters[vreg];
if (def->policy() == LDefinition::FIXED && def->output()->isArgument())
return def->output();
return new(alloc()) LStackSlot(DefaultStackSlot(vreg));
}
void
GreedyAllocator::findDefinitionsInLIR(LInstruction *ins)
{
for (size_t i = 0; i < ins->numDefs(); i++) {
LDefinition *def = ins->getDef(i);
JS_ASSERT(def->virtualRegister() < graph.numVirtualRegisters());
if (def->policy() == LDefinition::PASSTHROUGH)
continue;
vars[def->virtualRegister()].define(def, ins);
}
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition *temp = ins->getTemp(i);
JS_ASSERT(temp->virtualRegister() < graph.numVirtualRegisters());
JS_ASSERT(temp->policy() != LDefinition::PASSTHROUGH);
vars[temp->virtualRegister()].define(temp, ins);
}
}
bool
StupidAllocator::init()
{
if (!RegisterAllocator::init())
return false;
if (!virtualRegisters.reserve(graph.numVirtualRegisters()))
return false;
for (size_t i = 0; i < graph.numVirtualRegisters(); i++)
virtualRegisters.infallibleAppend(NULL);
for (size_t i = 0; i < graph.numBlocks(); i++) {
LBlock *block = graph.getBlock(i);
for (LInstructionIterator ins = block->begin(); ins != block->end(); ins++) {
for (size_t j = 0; j < ins->numDefs(); j++) {
LDefinition *def = ins->getDef(j);
if (def->policy() != LDefinition::PASSTHROUGH)
virtualRegisters[def->virtualRegister()] = def;
}
for (size_t j = 0; j < ins->numTemps(); j++) {
LDefinition *def = ins->getTemp(j);
if (def->isBogusTemp())
continue;
virtualRegisters[def->virtualRegister()] = def;
}
}
for (size_t j = 0; j < block->numPhis(); j++) {
LPhi *phi = block->getPhi(j);
LDefinition *def = phi->getDef(0);
uint32 vreg = def->virtualRegister();
virtualRegisters[vreg] = def;
}
}
// Assign physical registers to the tracked allocation.
{
registerCount = 0;
RegisterSet remainingRegisters(allRegisters_);
while (!remainingRegisters.empty(/* float = */ false))
registers[registerCount++].reg = AnyRegister(remainingRegisters.takeGeneral());
while (!remainingRegisters.empty(/* float = */ true))
registers[registerCount++].reg = AnyRegister(remainingRegisters.takeFloat());
JS_ASSERT(registerCount <= MAX_REGISTERS);
}
return true;
}
bool
AllocationIntegrityState::check(bool populateSafepoints)
{
MOZ_ASSERT(!instructions.empty());
#ifdef DEBUG
if (JitSpewEnabled(JitSpew_RegAlloc))
dump();
for (size_t blockIndex = 0; blockIndex < graph.numBlocks(); blockIndex++) {
LBlock* block = graph.getBlock(blockIndex);
// Check that all instruction inputs and outputs have been assigned an allocation.
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction* ins = *iter;
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next())
MOZ_ASSERT(!alloc->isUse());
for (size_t i = 0; i < ins->numDefs(); i++) {
LDefinition* def = ins->getDef(i);
MOZ_ASSERT(!def->output()->isUse());
LDefinition oldDef = instructions[ins->id()].outputs[i];
MOZ_ASSERT_IF(oldDef.policy() == LDefinition::MUST_REUSE_INPUT,
*def->output() == *ins->getOperand(oldDef.getReusedInput()));
}
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition* temp = ins->getTemp(i);
MOZ_ASSERT_IF(!temp->isBogusTemp(), temp->output()->isRegister());
LDefinition oldTemp = instructions[ins->id()].temps[i];
MOZ_ASSERT_IF(oldTemp.policy() == LDefinition::MUST_REUSE_INPUT,
*temp->output() == *ins->getOperand(oldTemp.getReusedInput()));
}
}
}
#endif
// Check that the register assignment and move groups preserve the original
// semantics of the virtual registers. Each virtual register has a single
// write (owing to the SSA representation), but the allocation may move the
// written value around between registers and memory locations along
// different paths through the script.
//
// For each use of an allocation, follow the physical value which is read
// backward through the script, along all paths to the value's virtual
// register's definition.
for (size_t blockIndex = 0; blockIndex < graph.numBlocks(); blockIndex++) {
LBlock* block = graph.getBlock(blockIndex);
for (LInstructionIterator iter = block->begin(); iter != block->end(); iter++) {
LInstruction* ins = *iter;
const InstructionInfo& info = instructions[ins->id()];
LSafepoint* safepoint = ins->safepoint();
if (safepoint) {
for (size_t i = 0; i < ins->numTemps(); i++) {
if (ins->getTemp(i)->isBogusTemp())
continue;
uint32_t vreg = info.temps[i].virtualRegister();
LAllocation* alloc = ins->getTemp(i)->output();
if (!checkSafepointAllocation(ins, vreg, *alloc, populateSafepoints))
return false;
}
MOZ_ASSERT_IF(ins->isCall() && !populateSafepoints,
safepoint->liveRegs().emptyFloat() &&
safepoint->liveRegs().emptyGeneral());
}
size_t inputIndex = 0;
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next()) {
LAllocation oldInput = info.inputs[inputIndex++];
if (!oldInput.isUse())
continue;
uint32_t vreg = oldInput.toUse()->virtualRegister();
if (safepoint && !oldInput.toUse()->usedAtStart()) {
if (!checkSafepointAllocation(ins, vreg, **alloc, populateSafepoints))
return false;
}
// Start checking at the previous instruction, in case this
// instruction reuses its input register for an output.
LInstructionReverseIterator riter = block->rbegin(ins);
riter++;
checkIntegrity(block, *riter, vreg, **alloc, populateSafepoints);
while (!worklist.empty()) {
IntegrityItem item = worklist.popCopy();
checkIntegrity(item.block, *item.block->rbegin(), item.vreg, item.alloc, populateSafepoints);
}
}
}
}
return true;
}
bool
LiveRangeAllocator<VREG>::buildLivenessInfo()
{
if (!init())
return false;
Vector<MBasicBlock *, 1, SystemAllocPolicy> loopWorkList;
BitSet *loopDone = BitSet::New(alloc(), graph.numBlockIds());
if (!loopDone)
return false;
for (size_t i = graph.numBlocks(); i > 0; i--) {
if (mir->shouldCancel("Build Liveness Info (main loop)"))
return false;
LBlock *block = graph.getBlock(i - 1);
MBasicBlock *mblock = block->mir();
BitSet *live = BitSet::New(alloc(), graph.numVirtualRegisters());
if (!live)
return false;
liveIn[mblock->id()] = live;
// Propagate liveIn from our successors to us
for (size_t i = 0; i < mblock->lastIns()->numSuccessors(); i++) {
MBasicBlock *successor = mblock->lastIns()->getSuccessor(i);
// Skip backedges, as we fix them up at the loop header.
if (mblock->id() < successor->id())
live->insertAll(liveIn[successor->id()]);
}
// Add successor phis
if (mblock->successorWithPhis()) {
LBlock *phiSuccessor = mblock->successorWithPhis()->lir();
for (unsigned int j = 0; j < phiSuccessor->numPhis(); j++) {
LPhi *phi = phiSuccessor->getPhi(j);
LAllocation *use = phi->getOperand(mblock->positionInPhiSuccessor());
uint32_t reg = use->toUse()->virtualRegister();
live->insert(reg);
}
}
// Variables are assumed alive for the entire block, a define shortens
// the interval to the point of definition.
for (BitSet::Iterator liveRegId(*live); liveRegId; liveRegId++) {
if (!vregs[*liveRegId].getInterval(0)->addRangeAtHead(inputOf(block->firstId()),
outputOf(block->lastId()).next()))
{
return false;
}
}
// Shorten the front end of live intervals for live variables to their
// point of definition, if found.
for (LInstructionReverseIterator ins = block->rbegin(); ins != block->rend(); ins++) {
// Calls may clobber registers, so force a spill and reload around the callsite.
if (ins->isCall()) {
for (AnyRegisterIterator iter(allRegisters_); iter.more(); iter++) {
if (forLSRA) {
if (!addFixedRangeAtHead(*iter, inputOf(*ins), outputOf(*ins)))
return false;
} else {
bool found = false;
for (size_t i = 0; i < ins->numDefs(); i++) {
if (ins->getDef(i)->isPreset() &&
*ins->getDef(i)->output() == LAllocation(*iter)) {
found = true;
break;
}
}
if (!found && !addFixedRangeAtHead(*iter, outputOf(*ins), outputOf(*ins).next()))
return false;
}
}
}
for (size_t i = 0; i < ins->numDefs(); i++) {
if (ins->getDef(i)->policy() != LDefinition::PASSTHROUGH) {
LDefinition *def = ins->getDef(i);
CodePosition from;
if (def->policy() == LDefinition::PRESET && def->output()->isRegister() && forLSRA) {
// The fixed range covers the current instruction so the
// interval for the virtual register starts at the next
// instruction. If the next instruction has a fixed use,
// this can lead to unnecessary register moves. To avoid
// special handling for this, assert the next instruction
// has no fixed uses. defineFixed guarantees this by inserting
// an LNop.
JS_ASSERT(!NextInstructionHasFixedUses(block, *ins));
AnyRegister reg = def->output()->toRegister();
if (!addFixedRangeAtHead(reg, inputOf(*ins), outputOf(*ins).next()))
return false;
from = outputOf(*ins).next();
} else {
from = forLSRA ? inputOf(*ins) : outputOf(*ins);
}
if (def->policy() == LDefinition::MUST_REUSE_INPUT) {
// MUST_REUSE_INPUT is implemented by allocating an output
// register and moving the input to it. Register hints are
// used to avoid unnecessary moves. We give the input an
// LUse::ANY policy to avoid allocating a register for the
// input.
LUse *inputUse = ins->getOperand(def->getReusedInput())->toUse();
JS_ASSERT(inputUse->policy() == LUse::REGISTER);
JS_ASSERT(inputUse->usedAtStart());
*inputUse = LUse(inputUse->virtualRegister(), LUse::ANY, /* usedAtStart = */ true);
}
LiveInterval *interval = vregs[def].getInterval(0);
interval->setFrom(from);
// Ensure that if there aren't any uses, there's at least
// some interval for the output to go into.
if (interval->numRanges() == 0) {
if (!interval->addRangeAtHead(from, from.next()))
return false;
}
live->remove(def->virtualRegister());
}
}
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition *temp = ins->getTemp(i);
if (temp->isBogusTemp())
continue;
if (forLSRA) {
if (temp->policy() == LDefinition::PRESET) {
if (ins->isCall())
continue;
AnyRegister reg = temp->output()->toRegister();
if (!addFixedRangeAtHead(reg, inputOf(*ins), outputOf(*ins)))
return false;
// Fixed intervals are not added to safepoints, so do it
// here.
if (LSafepoint *safepoint = ins->safepoint())
AddRegisterToSafepoint(safepoint, reg, *temp);
} else {
JS_ASSERT(!ins->isCall());
if (!vregs[temp].getInterval(0)->addRangeAtHead(inputOf(*ins), outputOf(*ins)))
return false;
}
} else {
// Normally temps are considered to cover both the input
// and output of the associated instruction. In some cases
// though we want to use a fixed register as both an input
// and clobbered register in the instruction, so watch for
// this and shorten the temp to cover only the output.
CodePosition from = inputOf(*ins);
if (temp->policy() == LDefinition::PRESET) {
AnyRegister reg = temp->output()->toRegister();
for (LInstruction::InputIterator alloc(**ins); alloc.more(); alloc.next()) {
if (alloc->isUse()) {
LUse *use = alloc->toUse();
if (use->isFixedRegister()) {
if (GetFixedRegister(vregs[use].def(), use) == reg)
from = outputOf(*ins);
}
}
}
}
CodePosition to =
ins->isCall() ? outputOf(*ins) : outputOf(*ins).next();
if (!vregs[temp].getInterval(0)->addRangeAtHead(from, to))
return false;
}
}
DebugOnly<bool> hasUseRegister = false;
DebugOnly<bool> hasUseRegisterAtStart = false;
for (LInstruction::InputIterator inputAlloc(**ins); inputAlloc.more(); inputAlloc.next()) {
if (inputAlloc->isUse()) {
LUse *use = inputAlloc->toUse();
// The first instruction, LLabel, has no uses.
JS_ASSERT(inputOf(*ins) > outputOf(block->firstId()));
// Call uses should always be at-start or fixed, since the fixed intervals
// use all registers.
JS_ASSERT_IF(ins->isCall() && !inputAlloc.isSnapshotInput(),
use->isFixedRegister() || use->usedAtStart());
#ifdef DEBUG
// Don't allow at-start call uses if there are temps of the same kind,
// so that we don't assign the same register.
if (ins->isCall() && use->usedAtStart()) {
for (size_t i = 0; i < ins->numTemps(); i++)
JS_ASSERT(vregs[ins->getTemp(i)].isDouble() != vregs[use].isDouble());
}
// If there are both useRegisterAtStart(x) and useRegister(y)
// uses, we may assign the same register to both operands due to
// interval splitting (bug 772830). Don't allow this for now.
if (use->policy() == LUse::REGISTER) {
if (use->usedAtStart()) {
if (!IsInputReused(*ins, use))
hasUseRegisterAtStart = true;
} else {
hasUseRegister = true;
}
}
JS_ASSERT(!(hasUseRegister && hasUseRegisterAtStart));
#endif
// Don't treat RECOVERED_INPUT uses as keeping the vreg alive.
if (use->policy() == LUse::RECOVERED_INPUT)
continue;
CodePosition to;
if (forLSRA) {
if (use->isFixedRegister()) {
AnyRegister reg = GetFixedRegister(vregs[use].def(), use);
if (!addFixedRangeAtHead(reg, inputOf(*ins), outputOf(*ins)))
return false;
to = inputOf(*ins);
// Fixed intervals are not added to safepoints, so do it
// here.
LSafepoint *safepoint = ins->safepoint();
if (!ins->isCall() && safepoint)
AddRegisterToSafepoint(safepoint, reg, *vregs[use].def());
} else {
to = use->usedAtStart() ? inputOf(*ins) : outputOf(*ins);
}
} else {
to = (use->usedAtStart() || ins->isCall())
? inputOf(*ins) : outputOf(*ins);
if (use->isFixedRegister()) {
LAllocation reg(AnyRegister::FromCode(use->registerCode()));
for (size_t i = 0; i < ins->numDefs(); i++) {
LDefinition *def = ins->getDef(i);
if (def->policy() == LDefinition::PRESET && *def->output() == reg)
to = inputOf(*ins);
}
}
}
LiveInterval *interval = vregs[use].getInterval(0);
if (!interval->addRangeAtHead(inputOf(block->firstId()), forLSRA ? to : to.next()))
return false;
interval->addUse(new(alloc()) UsePosition(use, to));
live->insert(use->virtualRegister());
}
}
}
// Phis have simultaneous assignment semantics at block begin, so at
// the beginning of the block we can be sure that liveIn does not
// contain any phi outputs.
for (unsigned int i = 0; i < block->numPhis(); i++) {
LDefinition *def = block->getPhi(i)->getDef(0);
if (live->contains(def->virtualRegister())) {
live->remove(def->virtualRegister());
} else {
// This is a dead phi, so add a dummy range over all phis. This
// can go away if we have an earlier dead code elimination pass.
if (!vregs[def].getInterval(0)->addRangeAtHead(inputOf(block->firstId()),
outputOf(block->firstId())))
{
return false;
}
}
}
if (mblock->isLoopHeader()) {
// A divergence from the published algorithm is required here, as
// our block order does not guarantee that blocks of a loop are
// contiguous. As a result, a single live interval spanning the
// loop is not possible. Additionally, we require liveIn in a later
// pass for resolution, so that must also be fixed up here.
MBasicBlock *loopBlock = mblock->backedge();
while (true) {
// Blocks must already have been visited to have a liveIn set.
JS_ASSERT(loopBlock->id() >= mblock->id());
// Add an interval for this entire loop block
CodePosition from = inputOf(loopBlock->lir()->firstId());
CodePosition to = outputOf(loopBlock->lir()->lastId()).next();
for (BitSet::Iterator liveRegId(*live); liveRegId; liveRegId++) {
if (!vregs[*liveRegId].getInterval(0)->addRange(from, to))
return false;
}
// Fix up the liveIn set to account for the new interval
liveIn[loopBlock->id()]->insertAll(live);
// Make sure we don't visit this node again
loopDone->insert(loopBlock->id());
// If this is the loop header, any predecessors are either the
// backedge or out of the loop, so skip any predecessors of
// this block
if (loopBlock != mblock) {
for (size_t i = 0; i < loopBlock->numPredecessors(); i++) {
MBasicBlock *pred = loopBlock->getPredecessor(i);
if (loopDone->contains(pred->id()))
continue;
if (!loopWorkList.append(pred))
return false;
}
}
// Terminate loop if out of work.
if (loopWorkList.empty())
break;
// Grab the next block off the work list, skipping any OSR block.
while (!loopWorkList.empty()) {
loopBlock = loopWorkList.popCopy();
if (loopBlock->lir() != graph.osrBlock())
break;
}
// If end is reached without finding a non-OSR block, then no more work items were found.
if (loopBlock->lir() == graph.osrBlock()) {
JS_ASSERT(loopWorkList.empty());
break;
}
}
// Clear the done set for other loops
loopDone->clear();
}
JS_ASSERT_IF(!mblock->numPredecessors(), live->empty());
}
validateVirtualRegisters();
// If the script has an infinite loop, there may be no MReturn and therefore
// no fixed intervals. Add a small range to fixedIntervalsUnion so that the
// rest of the allocator can assume it has at least one range.
if (fixedIntervalsUnion->numRanges() == 0) {
if (!fixedIntervalsUnion->addRangeAtHead(CodePosition(0, CodePosition::INPUT),
CodePosition(0, CodePosition::OUTPUT)))
{
return false;
}
}
return true;
}
void
StupidAllocator::allocateForInstruction(LInstruction *ins)
{
// Sync all registers before making a call.
if (ins->isCall()) {
for (size_t i = 0; i < registerCount; i++)
syncRegister(ins, i);
}
// Allocate for inputs which are required to be in registers.
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next()) {
if (!alloc->isUse())
continue;
LUse *use = alloc->toUse();
uint32_t vreg = use->virtualRegister();
if (use->policy() == LUse::REGISTER) {
AnyRegister reg = ensureHasRegister(ins, vreg);
alloc.replace(LAllocation(reg));
} else if (use->policy() == LUse::FIXED) {
AnyRegister reg = GetFixedRegister(virtualRegisters[use->virtualRegister()], use);
RegisterIndex index = registerIndex(reg);
if (registers[index].vreg != vreg) {
evictRegister(ins, index);
RegisterIndex existing = findExistingRegister(vreg);
if (existing != UINT32_MAX)
evictRegister(ins, existing);
loadRegister(ins, vreg, index);
}
alloc.replace(LAllocation(reg));
} else {
// Inputs which are not required to be in a register are not
// allocated until after temps/definitions, as the latter may need
// to evict registers which hold these inputs.
}
}
// Find registers to hold all temporaries and outputs of the instruction.
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition *def = ins->getTemp(i);
if (!def->isBogusTemp())
allocateForDefinition(ins, def);
}
for (size_t i = 0; i < ins->numDefs(); i++) {
LDefinition *def = ins->getDef(i);
if (def->policy() != LDefinition::PASSTHROUGH)
allocateForDefinition(ins, def);
}
// Allocate for remaining inputs which do not need to be in registers.
for (LInstruction::InputIterator alloc(*ins); alloc.more(); alloc.next()) {
if (!alloc->isUse())
continue;
LUse *use = alloc->toUse();
uint32_t vreg = use->virtualRegister();
JS_ASSERT(use->policy() != LUse::REGISTER && use->policy() != LUse::FIXED);
RegisterIndex index = findExistingRegister(vreg);
if (index == UINT32_MAX) {
LAllocation *stack = stackLocation(use->virtualRegister());
alloc.replace(*stack);
} else {
registers[index].age = ins->id();
alloc.replace(LAllocation(registers[index].reg));
}
}
// If this is a call, evict all registers except for those holding outputs.
if (ins->isCall()) {
for (size_t i = 0; i < registerCount; i++) {
if (!registers[i].dirty)
registers[i].set(MISSING_ALLOCATION);
}
}
}
bool
AllocationIntegrityState::checkIntegrity(LBlock *block, LInstruction *ins,
uint32_t vreg, LAllocation alloc, bool populateSafepoints)
{
for (LInstructionReverseIterator iter(block->rbegin(ins)); iter != block->rend(); iter++) {
ins = *iter;
// Follow values through assignments in move groups. All assignments in
// a move group are considered to happen simultaneously, so stop after
// the first matching move is found.
if (ins->isMoveGroup()) {
LMoveGroup *group = ins->toMoveGroup();
for (int i = group->numMoves() - 1; i >= 0; i--) {
if (*group->getMove(i).to() == alloc) {
alloc = *group->getMove(i).from();
break;
}
}
}
const InstructionInfo &info = instructions[ins->id()];
// Make sure the physical location being tracked is not clobbered by
// another instruction, and that if the originating vreg definition is
// found that it is writing to the tracked location.
for (size_t i = 0; i < ins->numDefs(); i++) {
LDefinition *def = ins->getDef(i);
if (def->policy() == LDefinition::PASSTHROUGH)
continue;
if (info.outputs[i].virtualRegister() == vreg) {
JS_ASSERT(*def->output() == alloc);
// Found the original definition, done scanning.
return true;
} else {
JS_ASSERT(*def->output() != alloc);
}
}
for (size_t i = 0; i < ins->numTemps(); i++) {
LDefinition *temp = ins->getTemp(i);
if (!temp->isBogusTemp())
JS_ASSERT(*temp->output() != alloc);
}
if (ins->safepoint()) {
if (!checkSafepointAllocation(ins, vreg, alloc, populateSafepoints))
return false;
}
}
// Phis are effectless, but change the vreg we are tracking. Check if there
// is one which produced this vreg. We need to follow back through the phi
// inputs as it is not guaranteed the register allocator filled in physical
// allocations for the inputs and outputs of the phis.
for (size_t i = 0; i < block->numPhis(); i++) {
InstructionInfo &info = blocks[block->mir()->id()].phis[i];
LPhi *phi = block->getPhi(i);
if (info.outputs[0].virtualRegister() == vreg) {
for (size_t j = 0; j < phi->numOperands(); j++) {
uint32_t newvreg = info.inputs[j].toUse()->virtualRegister();
LBlock *predecessor = graph.getBlock(block->mir()->getPredecessor(j)->id());
if (!addPredecessor(predecessor, newvreg, alloc))
return false;
}
return true;
}
}
// No phi which defined the vreg we are tracking, follow back through all
// predecessors with the existing vreg.
for (size_t i = 0; i < block->mir()->numPredecessors(); i++) {
LBlock *predecessor = graph.getBlock(block->mir()->getPredecessor(i)->id());
if (!addPredecessor(predecessor, vreg, alloc))
return false;
}
return true;
}
