Example #1
0
inline static MCDisassembler::DecodeStatus
addOperand(MCInst &Inst, const MCOperand& Opnd) {
  Inst.addOperand(Opnd);
  return Opnd.isValid() ?
    MCDisassembler::Success :
    MCDisassembler::SoftFail;
}
Example #2
0
static void CreateMCInst(MCInst& Inst, unsigned Opc, const MCOperand& Opnd0,
                         const MCOperand& Opnd1,
                         const MCOperand& Opnd2 = MCOperand()) {
  Inst.setOpcode(Opc);
  Inst.addOperand(Opnd0);
  Inst.addOperand(Opnd1);
  if (Opnd2.isValid())
    Inst.addOperand(Opnd2);
}
Example #3
0
void XCoreMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
  OutMI.setOpcode(MI->getOpcode());

  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    const MachineOperand &MO = MI->getOperand(i);
    MCOperand MCOp = LowerOperand(MO);

    if (MCOp.isValid())
      OutMI.addOperand(MCOp);
  }
}
void SampleMCInstLower::
Lower(const MachineInstr *MI, MCInst &OutMI) const {
  DEBUG(dbgs() << ">> SampleMCInstLower::Lower <<\n");
  OutMI.setOpcode(MI->getOpcode());

  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    const MachineOperand &MO = MI->getOperand(i);
    MCOperand MCOp = LowerOperand(MO);

    if (MCOp.isValid())
      OutMI.addOperand(MCOp);
  }
}
void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
  if (lowerLongBranch(MI, OutMI))
    return;

  OutMI.setOpcode(MI->getOpcode());

  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    const MachineOperand &MO = MI->getOperand(i);
    MCOperand MCOp = LowerOperand(MO);

    if (MCOp.isValid())
      OutMI.addOperand(MCOp);
  }
}
Example #6
0
void llvm::LowerSparcMachineInstrToMCInst(const MachineInstr *MI,
                                          MCInst &OutMI,
                                          AsmPrinter &AP)
{

  OutMI.setOpcode(MI->getOpcode());

  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
    const MachineOperand &MO = MI->getOperand(i);
    MCOperand MCOp = LowerOperand(MI, MO, AP);

    if (MCOp.isValid())
      OutMI.addOperand(MCOp);
  }
}
void NyuziMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
  OutMI.setOpcode(MI->getOpcode());

  // XXX note that this chunk of code assumes a load instruction. It's also
  // possible for MO_ConstantPoolIndex to appear in arithmetic.  In this
  // situation, the instruction would be clobbered.
  if (MI->getNumOperands() > 1 &&
      (MI->getOperand(1).getType() == MachineOperand::MO_ConstantPoolIndex ||
       MI->getOperand(1).getType() == MachineOperand::MO_JumpTableIndex)) {
    OutMI.addOperand(LowerOperand(MI->getOperand(0))); // result

    const MachineOperand &cpEntry = MI->getOperand(1);

    // This is a PC relative constant pool access.  Add the PC register
    // to this instruction to match what the assembly parser produces
    // (and InstPrinter/Encoder expects)
    // It should look like this:
    // <MCInst #97 LWi <MCOperand Reg:8> <MCOperand Reg:3> <MCOperand
    // Expr:(foo)>>
    OutMI.addOperand(MCOperand::CreateReg(Nyuzi::PC_REG));
    const MCSymbol *Symbol;
    if (MI->getOperand(1).getType() == MachineOperand::MO_ConstantPoolIndex)
      Symbol = AsmPrinter.GetCPISymbol(cpEntry.getIndex());
    else
      Symbol = AsmPrinter.GetJTISymbol(cpEntry.getIndex());

    const MCSymbolRefExpr *MCSym =
        MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, *Ctx);
    MCOperand MCOp = MCOperand::CreateExpr(MCSym);
    OutMI.addOperand(MCOp);
  } else {
    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
      const MachineOperand &MO = MI->getOperand(i);
      MCOperand MCOp = LowerOperand(MO);

      if (MCOp.isValid())
        OutMI.addOperand(MCOp);
    }
  }
}
Example #8
0
bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) {
  MCOp = MCInstLowering.LowerOperand(MO);
  return MCOp.isValid();
}