Example #1
0
bool Combiner::combineMachineInstrs(MachineFunction &MF) {
  // If the ISel pipeline failed, do not bother running this pass.
  // FIXME: Should this be here or in individual combiner passes.
  if (MF.getProperties().hasProperty(
          MachineFunctionProperties::Property::FailedISel))
    return false;

  MRI = &MF.getRegInfo();
  Builder.setMF(MF);

  DEBUG(dbgs() << "Generic MI Combiner for: " << MF.getName() << '\n');

  MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);

  bool MFChanged = false;
  bool Changed;

  do {
    // Collect all instructions. Do a post order traversal for basic blocks and
    // insert with list bottom up, so while we pop_back_val, we'll traverse top
    // down RPOT.
    Changed = false;
    GISelWorkList<512> WorkList;
    for (MachineBasicBlock *MBB : post_order(&MF)) {
      if (MBB->empty())
        continue;
      for (auto MII = MBB->rbegin(), MIE = MBB->rend(); MII != MIE;) {
        MachineInstr *CurMI = &*MII;
        ++MII;
        // Erase dead insts before even adding to the list.
        if (isTriviallyDead(*CurMI, *MRI)) {
          DEBUG(dbgs() << *CurMI << "Is dead; erasing.\n");
          CurMI->eraseFromParentAndMarkDBGValuesForRemoval();
          continue;
        }
        WorkList.insert(CurMI);
      }
    }
    // Main Loop. Process the instructions here.
    while (!WorkList.empty()) {
      MachineInstr *CurrInst = WorkList.pop_back_val();
      DEBUG(dbgs() << "Try combining " << *CurrInst << "\n";);
      Changed |= CInfo.combine(*CurrInst, Builder);
    }
    MFChanged |= Changed;
  } while (Changed);
bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
    if (skipOptnoneFunction(*MF.getFunction()))
        return false;

    bool AnyChanges = false;
    MRI = &MF.getRegInfo();
    TRI = MF.getSubtarget().getRegisterInfo();
    TII = MF.getSubtarget().getInstrInfo();

    // Loop over all instructions in all blocks, from bottom to top, so that it's
    // more likely that chains of dependent but ultimately dead instructions will
    // be cleaned up.
    for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
            I != E; ++I) {
        MachineBasicBlock *MBB = &*I;

        // Start out assuming that reserved registers are live out of this block.
        LivePhysRegs = MRI->getReservedRegs();

        // Add live-ins from sucessors to LivePhysRegs. Normally, physregs are not
        // live across blocks, but some targets (x86) can have flags live out of a
        // block.
        for (MachineBasicBlock::succ_iterator S = MBB->succ_begin(),
                E = MBB->succ_end(); S != E; S++)
            for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin();
                    LI != (*S)->livein_end(); LI++)
                LivePhysRegs.set(*LI);

        // Now scan the instructions and delete dead ones, tracking physreg
        // liveness as we go.
        for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
                MIE = MBB->rend(); MII != MIE; ) {
            MachineInstr *MI = &*MII;

            // If the instruction is dead, delete it!
            if (isDead(MI)) {
                DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
                // It is possible that some DBG_VALUE instructions refer to this
                // instruction.  They get marked as undef and will be deleted
                // in the live debug variable analysis.
                MI->eraseFromParentAndMarkDBGValuesForRemoval();
                AnyChanges = true;
                ++NumDeletes;
                MIE = MBB->rend();
                // MII is now pointing to the next instruction to process,
                // so don't increment it.
                continue;
            }

            // Record the physreg defs.
            for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
                const MachineOperand &MO = MI->getOperand(i);
                if (MO.isReg() && MO.isDef()) {
                    unsigned Reg = MO.getReg();
                    if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
                        // Check the subreg set, not the alias set, because a def
                        // of a super-register may still be partially live after
                        // this def.
                        for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
                                SR.isValid(); ++SR)
                            LivePhysRegs.reset(*SR);
                    }
                } else if (MO.isRegMask()) {
                    // Register mask of preserved registers. All clobbers are dead.
                    LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
                }
            }
            // Record the physreg uses, after the defs, in case a physreg is
            // both defined and used in the same instruction.
            for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
                const MachineOperand &MO = MI->getOperand(i);
                if (MO.isReg() && MO.isUse()) {
                    unsigned Reg = MO.getReg();
                    if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
                        for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
                            LivePhysRegs.set(*AI);
                    }
                }
            }

            // We didn't delete the current instruction, so increment MII to
            // the next one.
            ++MII;
        }
    }

    LivePhysRegs.clear();
    return AnyChanges;
}