MemberDef* VerilogDocGen::findDefinition(ClassDef *cd, QCString& memName){
MemberDef *md;
MemberList *ml= cd->getMemberList(MemberListType_variableMembers);
if(ml==NULL) return NULL;
MemberListIterator fmni(*ml);
for (fmni.toFirst();(md=fmni.current());++fmni)
{
if(md->getMemberSpecifiers()==VerilogDocGen::INCLUDE){
ClassDef* cdef= VhdlDocGen::getClass(md->name());
if(cdef){
MemberDef* mdd=VerilogDocGen::findMemberDef(cdef,memName,MemberListType_variableMembers,-1,false);
MemberList *ml= cdef->getMemberList(MemberListType_variableMembers);
assert(ml);
if(mdd) return mdd;
MemberListIterator fmni(*ml);
//assert(false);
}
}
}//for
return NULL;
}//findDefinition
void VerilogDocGen::writePlainVerilogDeclarations(MemberDef* mdef,MemberList* mlist,OutputList &ol,
ClassDef *cd,NamespaceDef *nd,FileDef *fd,GroupDef *gd,int specifier){
ol.pushGeneratorState();
bool first=TRUE;
MemberDef *md;
MemberListIterator mli(*mlist);
for ( ; (md=mli.current()); ++mli )
{
int mems=md->getMemberSpecifiers();
if (md->isBriefSectionVisible() && (mems==specifier))
{
if (first) ol.startMemberList(),first=FALSE;
VerilogDocGen::writeVerilogDeclarations(md,ol,cd,nd,fd,gd,false);
}//if
}//for
if (!first) ol.endMemberList();
}//plainDeclaration
